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emi-considerations-for-isolated-power-supplies

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EMI considerations for isolated power
supplies – how to test, troubleshoot &
resolve problems
Keith Keller
Analog Field Applications Engineer
Milwaukee WI
TI Information – Selective Disclosure
Presentation summary
•
•
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Background – EMI standards, test setup, LISN, detector types, etc.
Fundamental causes of Differential-mode (DM) & Common-mode (CM) EMI
Mitigation options to deal with DM & CM noise
Tips for troubleshooting & debug
Practical examples throughout
•
Based on PMP21479 65-W USB-PD Active-clamp-Flyback topology
What you’ll learn:
• Understand what causes EMI
• Understand the sources and causes of parasitic elements in EMI filter component, PCB’s and throughout
the board assembly
• Learn practical techniques to test, debug & root-cause EMI issues
• Learn how transformer construction influences EMI
• See real-world examples of how to resolve EMI issues
TI Information – Selective Disclosure
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EMI – where do I start?
• I built my prototype PSU, and resolved all functional issues
• I ran first-pass EMI scan – and my design fails badly!
– How can I fix the EMI?
– Where do I start?
• This presentation will help to show how you can get to a
result like this without necessarily adding a big EMI filter
47 dB
TI Information – Selective Disclosure
EMI background – standards & test setup
TI Information – Selective Disclosure
What are EMC & EMI & EMS?
• EMC = Electro Magnetic Compatibility
• EMI = Electro Magnetic Interference (emission)
• EMS = Electro Magnetic Susceptibility (immunity)
EMI
EMS
CS = Conducted Immunity
RS = Radiated Immunity
ESD = Electrostatic discharge
EFT/B = Electrical Fast Transient/Burst Immunity
SURGE
PFMF = Power Frequency Magnetic fields
DIP (Voltage variations)
EMC
TI Information – Selective Disclosure
In this topic only
CE = Conducted Emission
RE = Radiated Emission
Harmonic distortion
Fluctuation and Flicker
Reference: https://en.wikipedia.org/wiki/Electromagnetic_compatibility
5
EMC standards
• Standards for power supplies
REQUIREMENT
EMI
EMS
PARAMETERS
Emissions (RE & CE)
EN55032 (/CISPR 32)
Harmonic
EN61000-3-2
Fluctuation and flicker
EN61000-3-3
ESD
EN61000-4-2
RS
EN61000-4-3
EFT
EN61000-4-4
Surge
EN61000-4-5
CS
EN61000-4-6
PFMF
EN61000-4-8
DIP
EN61000-4-11
In this topic only
Reference: https://www.us.tdk-lambda.com/media/292070/tdk-lambda-blog-110507.pdf
TI Information – Selective Disclosure
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Conducted Emissions (CE) standards
• Summary of main product standards for conducted emissions
Product sector
CISPR standard
EN standard
FCC standard
Automotive
CISPR 25
EN 55025
--
Multimedia
CISPR 32
EN 55032
Part 15
ISM
CISPR 11
EN 55011
Part 18
CISPR 14-1
EN 55014-1
--
CISPR 15
EN 55015
Part 15/18
Household appliances,
electric tools and
similar apparatus
Lighting equipment
Reference:
Timothy Hegarty, “An overview of conducted EMI specifications for power supplies”,
http://www.ti.com/lit/wp/slyy136/slyy136.pdf
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How Conducted EMI is measured
• Horizontal & vertical ground planes
– (or screened room)
Vertical Ground Plane
• Equipment Under Test (EUT) on nonconductive table
• EUT powered through LISN
– (Line Impedance Stabilisation Network)
• Measure HF emissions from LISN
[1] EN55022, 2010, “Information technology equipment – Radio disturbance characteristics – Limits and methods of measurement”
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What is the purpose of the LISN?
50µH
L1
L2
Inoise/ITotal
Total input currents
LISN
AC/DC or DC/DC
Converter
Current for power50µH
Load
Noise Source
1µF
1µF
0.1µF
0.1µF
Noise current
50Ω
50Ω
G
Ground Plane
• LISN measurement output is a high-pass filter
• Low frequency power current passes straight through from AC source
• High frequency current (noise) is trapped by the LISN capacitor and the amplitude is
measured based on the voltage across 50Ω load -> measured by EMI receiver
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LISN – Line Impedance Stabilisation Network
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•
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Presents stable, consistent & repeatable line source impedance
Separation of power source noise
“Total” noise levels measured separately on L1 (Live) and L2 (Neutral)
Terminated into 50, internal to EMI receiver
EMI receiver
50Ω terminator provided by
EMI receiver
** Functional equivalent circuit of a LISN, not a complete schematic **
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EMI Receiver – Detector Types
Built-in detectors – peak, quasi-peak, average
SW
Peak
Noise
Measurement
Quasi-peak
Noise
Measurement
V
Average
Time
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EN55022/32 Limit Lines – Conducted Emissions
Class A and Class B limits, quasi-peak & average, 150kHz–30MHz
Class B
Class A
(Residential, commercial & light industrial)
(Heavy industrial)
(PC, notebook adapter)
[1] EN55022, 2010, “Information technology equipment – Radio disturbance characteristics – Limits and methods of measurement”
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LISN + EMI Filter + Power Supply
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LISN + EMI Filter + Power Supply
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–
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LISN + EMI Filter + Power Supply
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LISN + EMI Filter + Power Supply
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EMI debug & improvement
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EMI Fundamentals – Component Parasitics
• Parasitic elements are the cause of EMI
• If all components were ideal, there would be
no EMI issues
• EMI noise is generated by parasitic elements:
– ESR (equivalent series resistance)
– ESL (equivalent series inductance)
– Parasitic capacitances
• EMI noise is coupled & propagated through
parasitic elements:
– Capacitive coupling
– Inductive coupling
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Why care about Differential-Mode (DM) EMI?
• DM noise couples to the AC utility supply network
• Long AC distribution cables – act as good dipole antenna
• Will inadvertently radiate switching noise and interfere with radio communications
Radiated interference
Switching PSU
L
N
AC mains
distribution
cables
DM noise
source
Load
Radiated interference
TI Information – Selective Disclosure
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How is DM EMI generated?
• Switching ripple current produces ripple voltage across ESR (& ESL)
–
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• Ripple voltage is the DM noise that needs to be attenuated/filtered
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Mitigation options for DM noise
• Include EMI at the design phase
– Design & component choices to minimise DM EMI signal amplitude to be filtered
– Chose frequency, inductance, etc. to minimise pk-pk ripple current
 Power Stage Designer Software
– Choose capacitors with low esr to minimise pk-pk ripple voltage
– Good PCB layout important to minimise EMI
• Design DM LC filter to reduce the ripple that gets onto the AC line input
– DM signal can be easily simulated/analysed and DM filter can be calculated/simulated
–
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Power Stage Design SW
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DM filter design methodology
• Time-domain current waveform easy to measure or simulate
• Fourier Series expansion of switching current
– Convert waveform into harmonic components
• Or sample current waveform
– Use Fourier Transform to determine harmonics
• Establish required attenuation at each frequency
– To get sufficient margin below the relevant EMI limit
• Design the DM filter to achieve required attenuation
– Need to check all frequencies of interest
• Filter size is usually defined by the lowest frequency
switching harmonic that falls within the conducted
EMI band
– Typically EMI starts at 150 kHz for AC-DC PSU
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DM filter practical considerations
• DM filter requires high attenuation over wide bandwidth
AC voltage
– Example, peak PSU current amplitude typically several amps
– At 50 dBV, current in LISN 50-ohm resistor only ~6.3 uA
Ipeak (non-PFC)
Ipeak (with PFC)
• DM inductor passes the full AC line current
– Beware inductance roll-off with DC-bias
– Must not saturate to be effective – needs high current rating
– Consider the peak line current for non-PFC – high crest factor
• DM filter located close to switching PSU, with fast changing
magnetic fields – beware filter bypassing or noise coupling
• Parasitic capacitance across DM inductor is important –
reduces effectiveness at high frequency
– E.g. to filter 300 kHz component, could set LC freq ~30 kHz -> expect
~40 dB attenuation at 300 kHz, but parasitic cap => more like 30 dB
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Why care about Common-Mode (CM) EMI?
• Again, AC distribution cables and output load cables act as good dipole antenna
• CM noise will radiate from the cables and interfere with radio communications
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How is CM EMI generated?
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• Switching voltage across parasitic capacitance causes CM current flow to earth
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How is CM EMI generated?
• Switching voltage across parasitic capacitance causes CM current flow to earth
Vac
–
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+
CM EMI
Voltage
Z
EARTH
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Mitigation options for CM noise
1. Shielding:
reduce flow of HF current to EARTH
2. Cancellation:
arrange transformer and power stage for
balanced CM
3. Filtering:
increase impedance of the EARTH return
path and provide alternative routes for the
HF current
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CM mitigation by shielding
1. Shielding inside the transformer
– Internal shields between pri & sec
2. Shielding outside the transformer
– GNDed flux-band
3. Shielding of noisy circuit nodes
– GNDed heatsinks over/around high-voltage
switching nodes
4. Shielding of EMI filter from switching circuit
– GNDed shields/enclosures around filter
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CM mitigation by cancellation/balance
• Single-ended topologies – need explicit additional
cancellation elements (flyback & forward)
– Generate voltage proportional to CM waveform,
with opposite phase
– Capacitor to inject cancelling current to balance CM
– Can be explicit physical capacitor added to design
– Or can use parasitic cap, part of transformer structure
• Double-ended switching topologies – inherently
balanced for CM (push-pull, half-bridge & full-bridge)
Np1
• Single-ended topology alternatives
– Can position switches/rectifiers in middle of single-ended
windings to improve CM balance
– But difficult to level-shift drive, balance parasitic cap, etc.
Ns1
Icm1
Icm2
Np2
Ns2
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CM mitigation by filtering
• CM filter uses high impedance CM chokes and low-impedance Y-capacitors
• CM choke limits the flow of CM current from Earth
–
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• Y-cap provides low-impedance to keep CM current local to primary GND and away from Earth
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How to separate CM & DM noise
• Useful to observe CM & DM separately
– Just CM issue, or just DM, or both?
• Sophisticated method:
– LISN with dual output (L & N) or two single-line LISN’s
– Use DM & DM power splitters/combiners to attenuate
one or other noise type
• Simple (low-cost) methods:
– Add large X-capacitor upstream of the UUT
• Attenuate DM, leave mostly CM
– Use large Y-capacitor – attenuate CM, leave mostly DM
– Observe the baseline CM being coupled to the secondary side in the time-domain
Can be very insightful
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Observing the time-domain CM signal at the output
• Observe time-domain CM signal on scope, very informative
– Remove Y-cap temporarily
(maximise observable signal amplitude)
– Power UUT through LISN, with resistor loads
– Coil several turns of wire around the load
cables (sensing/pick-up coil)
– Connect scope earth lead to LISN earth
– Connect scope tip to sensing coil
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Interpretation of time-domain CM signal
• Will see “switch-node” shaped waveform –
capacitively-coupled to output
• Large pk-pk amplitude => bad CM noise
• Will require significant CM filtering to suppress
• Small pk-pk amplitude => good CM noise
• “Balanced” structure for low CM
• Will require much smaller CM filter
• Residual HF “spikes” => should only need small
HF CM choke
TI Information – Selective Disclosure
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CM filter choke practical considerations
• Freq response of core material
– High- cores –> high L @ low freq, but roll off fast at high freq
– High-freq cores –> low-, smaller L value @ low freq, better vs freq
– Sometimes need to use 2 CM chokes, 1 for LF & 1 for HF
• Split-wound vs bifilar-wound toroid
– Split-wound popular, lower cost, “free” DM choke from leakage
– Bifilar –> 1-side insulated wire, higher cost, but better noise immunity
• Parasitic input-output cap – multi-layer windings
– Multi-layer –> more turns, more L –> but also higher parasitic cap
• High input-output cap => lower self-resonant freq, worse @ HF
– Less layers => lower L, but also lower cap
– Sectional bobbins – used to reduce input-output parasitic capacitance
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CM filter choke winding example
• Split-wound 2 layer:
– 25T, 5.1 mH
– Excess pass margin @ LF
– Low pass margin @ 15 MHz
• Bifilar-wound 1 layer:
–
–
–
–
14T, 1.1 mH
Low input-output cap
Lower L at low freq, but better at HF
Better balance across frequency span
CM choke inductance vs freq
–
–
–
–
14T, 1.4 mH
Low input-output cap
Lower L at low freq, but better at HF
Better balance across frequency span
L (mH)
• Split-wound 1-layer:
6
5
4
3
2
1
0
2L, split
1L, split
1L, bifilar
0
200
400
600
Frequency (kHz)
800
1000
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CM choke example
Initial split-wound choke had EMI issues due to asymmetric noise
coupling from transformer – causes big difference in EMI on L vs N
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CM choke example
Changed to bifilar-wound choke, much
better EMI – much better noise immunity
12 dB
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Transformer internal shielding
• Shield added to keep most of CM current local to primary
• Shield is 1-turn winding => lower induced voltage, less voltage across
capacitance between shield & sec => less CM current flows
• Shield must be thin –> minimise induced eddy currents loss; significant as Fsw
increases
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Transformer CM noise example
• Typical interleaved Flyback transformer construction
• Primary (green), secondary (blue), auxiliary bias (red)
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Transformer CM noise example
• Typical connections to the Flyback power stage
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Transformer CM noise example
• Typical waveforms
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Transformer CM balance example
• Move auxiliary in-between inner Pri-SEC, add more turns & strands to fill layer
• Add foil shield (purple) in-between outer Pri-SEC
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Transformer CM balance example
• Connections to Flyback power stage
• Shield connects to tap on auxiliary bias winding
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Transformer CM balance example
• Waveforms – now don’t care about primary layers, only the aux & shield
• Aux & shield waveforms have same shape, amplitude & phase as secondary
→ balanced
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Transformer “housekeeping” best practices
• Centre-leg air-gaps only – outer legs will radiate
• “Noisier” windings on inside of layer structure
• GND ferrite core to local primary GND – large Cparasitic
• Flux-band to minimise stray coupling
– GNDing & flux-banding can give >10 dB improvement!
• Trade-off between interleaving for low leakage
inductance vs. low inter-winding parasitic capacitance
• Beware internal construction details:
Fluxband +
EMI shield
~14 dB
– Different parasitic pri-sec capacitance
– Different average CM voltage across the pri-sec capacitance
– Arrange winding layers to minimise voltage difference
• Minimise CM current through parasitic cap between layers
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PCB layout tips
• Detailed Layout Discussion in Tech Day 2018
• Minimise area of traces with high dv/dt –
minimise parasitic capacitance
• Minimise area of loops with high di/dt current
• Place filter components away from noise sources
• No GND plane under EMI filter
• CM choke input/output pins do not cross
• No GND plane under EMI filter
• Wide spacing between traces minimises parasitic
coupling capacitance
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PMP21479 65-W ACF USB-PD
• Improve transformer structure for CM balance
• Add transformer grounding & flux-banding + EMI shield
• Improve CM choke position/location/type
• Improve output cap position/location, PCB orientation
– Largely “free” improvements
– Little or no added cost or efficiency penalty
47 dB
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Summary & Conclusions
• Consider EMI right from the start – inherent part of the power supply design
• Minimise DM & CM EMI noise at source
• DM filter can be designed/calculated/simulated more easily than CM
• CM balance important as much as practically possible
• Debug to establish if EMI issue is CM or DM or both
• Assess CM performance in time-domain
• For isolated PSU transformer is most important component
– Internal construction details, CM balance, shielding, parasitic capacitance, house-keeping
• EMI filter components – be aware of parasitics and HF effects
• PSU layout and component placement – be aware of stray coupling paths
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