8 PAGE D C B A [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] 7 6 CONTENTS COVER PAGE SOC, PCIEX + CLOCKS + VIDEO SOC POWER, MEM+CPUCORE+MEMCORE+NBCORE+MISC SOC POWER, V_GFXCORE + VSS SOC, MEMOERY PARTITION C + D SOC, MEMORY PARTITION A + B SOC, VSS + SPARE SOC, DEBUG + SB SIGNALS SOC, DECOUPLING SOC, DECOUPLING SOC, DECOUPLING MEMORY CHANNEL D MEMORY CHANNEL D MEMORY CHANNEL D, DECOUPLING MEMORY CHANNEL C MEMORY CHANNEL C MEMORY CHANNEL C, DECOUPLING MEMORY CHANNEL B MEMORY CHANNEL B MEMORY CHANNEL B, DECOUPLING MEMORY CHANNEL A MEMORY CHANNEL A MEMORY CHANNEL A, DECOUPLING KIC, USB KIC, PCIEX + SATA + VIDEO KIC, SMC KIC, FACET KIC, POWER KIC, CLOCKS + STRAPPING + POR KIC, POWER KIC, DECOUPLING CONTROLLER, ETHERNET EMMC CONN, RJ45 + TOSLINK CONN, USB CONN, USB CONN, HDMI IN 5 [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58] [59] [60] [61] [62] [63] [64] [65] [66] [67] [68] [69] [70] [71] [72] 4 3 2 1 GREYBULL CONN, HDMI OUT CONN, ODD + HDD CONN, LITHIUM + FAN CONN, PWR VREGS, BLEEDERS VREGS, INPUT + OUTPUT FILTERS VREGS, CPUCORE VREGS, GFXCORE VREGS, GFXCORE OUTPUT PHASE 1 & 2 VREGS, GFXCORE OUTPUT PHASE 3 & 4 VREGS, CPUCORE OUTPUT PHASE VREGS, VTT TERMINATION VREGS, NBCORE VREGS, MEMCORE VREGS, MEMIOCD VREGS, MEMIOAB VREGS, V5P0 VREGS, V5P0 DUAL VREGS, V3P3 VREGS, VSOCPHY VREGS, VSOCPLL + VBURN + VFUSE + VBAT VREGS, VSB2P5 VREGS, VSB1P8PLL + VSB1P8IO + VSBCORE + VSB1P1PLL VREGS, STANDBY SWITCHERS 3P3 VREGS, STANDBY SWITCHERS 1P1 + 1P8 IR BLASTER I2C FACET, FTDI FACET, FTDI + MISC CONN, SWITCHES CONN, HDT DEBUG, VR HEADERS AND TEST POINTS DEBUG, CONNECTORS DEBUG, ENET EEPROM + MISC LABELS AND MOUNTING REV 1.0 FAB M RETAIL D C B RULES: (APPLIED WHEN POSSIBLE) 1.) MSB TO LSB IS TOP TO BOTTOM 2.) WHEN POSSIBLE: INPUTS ON LEFT, OUTPUTS ON RIGHT 3.) ORDER OF PAGES=CHIP INTERFACES, TERMINATION, POWER, DECOUPLING 4.) AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS 5.) LANED SIGNALS ARE GROUPED ON SYMBOLS 6.) TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS 7.) SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES 8.) SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS 9.) UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE 10.) SUFFIX _N FOR ACTIVE LOW OR N JUNCTION 12.) SUFFIX _P FOR P JUNCTION 13.) SUFFIX _EN FOR ENABLE 14.) 'CLK' FOR CLOCKS, 'RST' FOR RESETS 15.) PWRGD FOR POWER GOOD 16.) REV AND FAB ARE SET USING CUSTOM VARIABLES TOOLS>OPTIONS>VARIABLES A MICROSOFT Fri May 10 13:22:55 CONFIDENTIAL 2013 [PAGE_TITLE=COVER PAGE] 8 7 DRAWING 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 1/72 2 CSA PAGE 1/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 SOC,PCIEX + CLOCKS + VIDEO 1 R4R19 1 2 0 OHM 5% 402 EMPTY D D R4R20 1 2 0 OHM 5% 402 EMPTY IC U7E1 R5U6 1 2 0 OHM 5% 402 EMPTY PCIE 1 of 17 1 R5U7 1 2 0 OHM 5% EMPTY 402 AP20 PEX_SOC_SPARE_TP AP21 PEX_SOC_SPARE_TN PEX_SPARE_SOC_TP_C PEX_SPARE_SOC_TN_C AR19 AR20 P_UMI_RX3_P P_UMI_RX3_N P_UMI_TX2_P P_UMI_TX2_N AP23 PEX_SOC_ENET_TP AP24 PEX_SOC_ENET_TN 32 32 IN IN PEX_ENET_SOC_TP_C PEX_ENET_SOC_TN_C AN21 AN22 P_UMI_RX2_P P_UMI_RX2_N P_UMI_TX1_P P_UMI_TX1_N AU23 PEX_L1_SOC_SB_TP AU24 PEX_L1_SOC_SB_TN 25 25 IN IN PEX_L1_SB_SOC_TP_C PEX_L1_SB_SOC_TN_C AV22 AV23 P_UMI_RX1_P P_UMI_RX1_N P_UMI_TX0_P P_UMI_TX0_N AV25 PEX_L0_SOC_SB_TP AV26 PEX_L0_SOC_SB_TN IN IN PEX_L0_SB_SOC_TP_C PEX_L0_SB_SOC_TN_C AT24 AT25 P_UMI_RX0_P P_UMI_RX0_N P_RX_ZVDD_095 P_TX_ZVDD_095 X862035-001 BGA1443 EMPTY 29 29 29 29 29 29 29 29 1 C7E8 2 SOC_NB_PEX_SS_100M_CLKP SOC_NB_PEX_SS_100M_CLKN AU26 AU27 CLKIN_NB_P CLKIN_NB_N IN IN IN IN IN IN SOC_REF_NS_100M_CLKP SOC_REF_NS_100M_CLKN SOC_AV_NS_100M_CLKP SOC_AV_NS_100M_CLKN SOC_PEX_SS_100M_CLKP SOC_PEX_SS_100M_CLKN AT21 AT22 AV19 AV20 AU20 AU21 AR23 AR22 DISP_CLKIN_P DISP_CLKIN_N AV_CLKIN_P AV_CLKIN_N CLKIN_P CLKIN_N TEST25_P TEST25_N 1 R3T6 25 25 25 X862035-001 C7E5 2 C7E3 2 C7E1 2 DVI PCB ROUTING ORDERING TMDS CLOCK - TEST25_P TEST25_N [PAGE_TITLE=SOC PAGE 1] 8 7 MS_PART# U7E1 32 PEX_L1_SOC_SB_TP_C OUT 25 PEX_L1_SOC_SB_TN_C 0.1 UF 10% 6.3 V X5R 402 0.1 UF10% 6.3 V X5R C7E7 1 2 402 IN DP_AUX_SB_SOC_TN_C OUT DP1_HPD IN DP0_HPD 1 C3R26 1 25 PEX_L0_SOC_SB_TN_C OUT 25 25 25 38 38 38 38 25 25 38 38 2 0.1 UF 10% 6.3 V C3R25 1 2 X5R 402 0.1 UF 10% 6.3 V X5R 402 DP PCB ROUTING ORDERING PIN NAME DP LANE 3 - DP0_TX3_N TMDS CLOCK + DP LANE 3 + DP0_TX3_P TMDS DATA0 - DP LANE 2 - DP0_TX2_N TMDS DATA0 + DP LANE 2 + DP0_TX2_P TMDS DATA1 - DP LANE 1 - DP0_TX1_N TMDS DATA1 + DP LANE 1 + DP0_TX1_P TMDS DATA2 - DP LANE 0 - DP0_TX0_N TMDS DATA2 + DP LANE 0 + DP0_TX0_P MATL EMPTY 6 REF_DES EMPTY 100 KOHM 1% 2 CH 402 5 IN IN OUT OUT OUT OUT IN IN OUT OUT DP_CR_CLK AP14 DP_CR_CLK DP_L0_SB_SOC_TP_C DP_L0_SB_SOC_TN_C TMDS_TX_DP0 TMDS_TX_DN0 TMDS_TX_DP2 TMDS_TX_DN2 DP_L1_SB_SOC_TP_C DP_L1_SB_SOC_TN_C TMDS_TX_DP1 TMDS_TX_DN1 AU18 AU17 AU15 AU14 AV17 AV16 AT19 AT18 AT16 AT15 DP1_RX0_P DP1_RX0_N DP0_TX2_P DP0_TX2_N DP0_TX0_P DP0_TX0_N DP1_RX1_P DP1_RX1_N DP0_TX1_P DP0_TX1_N DP_AUX_SOC_SB_TP DP_AUX_SOC_SB_TN AT13 AT12 DP1_AUX_P DP1_AUX_N 38 38 38 38 OUT BI OUT OUT HDMI_OUT_DDC_CLK HDMI_OUT_DDC_DATA TMDS_TX_CLKP TMDS_TX_CLKN AR14 AR13 AV14 AV13 AP15 DP0_AUX_P DP0_AUX_N DP0_TX3_P DP0_TX3_N DP1_HPD 34 OUT SPDIF_OUT AP12 AU12 SPDIF_OUT DP0_HPD AM12 AR12 AN13 DP_TX_ZVSS DP_AUX_ZVSS DP_RX_ZVSS DP_TX_CALR DP_AUX_CALR DP_RX_CALR R3R11 100 KOHM 1% 2 CH 402 1 R3R10 150 OHMS 1% 2 CH 402 TRUEDESCR. DUMMY_BOM SOC R7D10 1 R3R7 150 OHMS 1% 2 CH 402 1 3 BGA1443 A 2 KOHM 1% 2 CH 402 DRAWING Tue Jun 18 16:42:23 2013 CONFIDENTIAL 4 B X862035-001 R3R9 MICROSOFT BOM PROPERTY C 25 OUT BI DP_AUX_SB_SOC_TP_C OUT PEX_L0_SOC_SB_TP_C 0.1 UF 10% 6.3 V X5R 402 IN IC U7E1 VIDEO 3 of 17 0.1 UF 10% 6.3 V X5R 402 1 OUT OUT OUT BGA1443 38 70 70 PEX_SOC_ENET_TN_C CLOCKS 2 of 17 IN IN A 32 IC U7E1 B OUT 10% 1 1 1 PEX_SOC_ENET_TP_C 0.1 UF 10% 6.3 V X5R 402 1 KOHM 1% CH 2 1 R3T5 402 1.69 KOHM 1% 2 CH 402 V_SOCPHY 2 0.1 UF 6.3 V X5R 402 AN19 AN18 RX_ZVDD_095 25 25 TX_ZVDD_095 C P_UMI_TX3_P P_UMI_TX3_N C7E6 PROJECT NAME PAGE GREYBULL_RETAIL 2/72 2 CSA PAGE 2/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 SOC POWER, MEM + CPUCORE + MEMCORE + NBCORE + MISC D D V_NBCORE EMPTY V_CPUCORE V_MEMIOCD V_MEMIOAB U7E1 IC C B VDD_MEM1[47] VDD_MEM1[46] VDD_MEM1[45] VDD_MEM1[44] VDD_MEM1[43] VDD_MEM1[42] VDD_MEM1[41] VDD_MEM1[40] VDD_MEM1[39] VDD_MEM1[38] VDD_MEM1[37] VDD_MEM1[36] VDD_MEM1[35] VDD_MEM1[34] VDD_MEM1[33] VDD_MEM1[32] VDD_MEM1[31] VDD_MEM1[30] VDD_MEM1[29] VDD_MEM1[28] VDD_MEM1[27] VDD_MEM1[26] VDD_MEM1[25] VDD_MEM1[24] VDD_MEM1[23] VDD_MEM1[22] VDD_MEM1[21] VDD_MEM1[20] VDD_MEM1[19] VDD_MEM1[18] VDD_MEM1[17] VDD_MEM1[16] VDD_MEM1[15] VDD_MEM1[14] VDD_MEM1[13] VDD_MEM1[12] VDD_MEM1[11] VDD_MEM1[10] VDD_MEM1[9] VDD_MEM1[8] VDD_MEM1[7] VDD_MEM1[6] VDD_MEM1[5] VDD_MEM1[4] VDD_MEM1[3] VDD_MEM1[2] VDD_MEM1[1] VDD_MEM1[0] X862035-001 VDD_MEM0[47] VDD_MEM0[46] VDD_MEM0[45] VDD_MEM0[44] VDD_MEM0[43] VDD_MEM0[42] VDD_MEM0[41] VDD_MEM0[40] VDD_MEM0[39] VDD_MEM0[38] VDD_MEM0[37] VDD_MEM0[36] VDD_MEM0[35] VDD_MEM0[34] VDD_MEM0[33] VDD_MEM0[32] VDD_MEM0[31] VDD_MEM0[30] VDD_MEM0[29] VDD_MEM0[28] VDD_MEM0[27] VDD_MEM0[26] VDD_MEM0[25] VDD_MEM0[24] VDD_MEM0[23] VDD_MEM0[22] VDD_MEM0[21] VDD_MEM0[20] VDD_MEM0[19] VDD_MEM0[18] VDD_MEM0[17] VDD_MEM0[16] VDD_MEM0[15] VDD_MEM0[14] VDD_MEM0[13] VDD_MEM0[12] VDD_MEM0[11] VDD_MEM0[10] VDD_MEM0[9] VDD_MEM0[8] VDD_MEM0[7] VDD_MEM0[6] VDD_MEM0[5] VDD_MEM0[4] VDD_MEM0[3] VDD_MEM0[2] VDD_MEM0[1] VDD_MEM0[0] POWER U7E1 IC VDD_CORE 10 of 17 A31 A30 A29 A27 A25 B31 B30 B29 B27 B25 C30 C28 C26 D28 D26 E29 E27 E25 F29 F27 F25 G28 G26 H28 H26 J27 J25 K27 K25 L28 L26 M28 M26 N27 N25 P27 P25 R28 R26 T28 T26 U27 U25 V27 V25 W28 W26 Y28 Y26 AA27 AA25 AB27 AB25 AC28 AC26 VDD MEM 9 of 17 AU31 AU35 AT30 AT34 AP29 AP33 AN28 AN32 AN37 AM36 AK33 AJ34 AJ37 AH29 AH36 AF29 AF33 AE34 AE37 AD29 AD36 AB29 AB33 AA34 AA37 Y29 Y36 V29 V33 U34 U37 T29 T36 P29 P33 N34 N37 M29 M36 K29 K33 J34 J37 H29 H36 F33 E32 E34 IC U7E1 EMPTY EMPTY EMPTY AU4 AU8 AT5 AT9 AP6 AP10 AN2 AN7 AN11 AM3 AK6 AJ2 AJ5 AH3 AH10 AF6 AF10 AE2 AE5 AD3 AD10 AB6 AB10 AA2 AA5 Y3 Y10 V6 V10 U2 U5 T3 T10 P6 P10 N2 N5 M3 M10 K6 K10 J2 J5 H3 H10 F6 E5 E7 VDD_CORE[54] VDD_CORE[53] VDD_CORE[52] VDD_CORE[51] VDD_CORE[50] VDD_CORE[49] VDD_CORE[48] VDD_CORE[47] VDD_CORE[46] VDD_CORE[45] VDD_CORE[44] VDD_CORE[43] VDD_CORE[42] VDD_CORE[41] VDD_CORE[40] VDD_CORE[39] VDD_CORE[38] VDD_CORE[37] VDD_CORE[36] VDD_CORE[35] VDD_CORE[34] VDD_CORE[33] VDD_CORE[32] VDD_CORE[31] VDD_CORE[30] VDD_CORE[29] VDD_CORE[28] VDD_CORE[27] VDD_CORE[26] VDD_CORE[25] VDD_CORE[24] VDD_CORE[23] VDD_CORE[22] VDD_CORE[21] VDD_CORE[20] VDD_CORE[19] VDD_CORE[18] VDD_CORE[17] VDD_CORE[16] VDD_CORE[15] VDD_CORE[14] VDD_CORE[13] VDD_CORE[12] VDD_CORE[11] VDD_CORE[10] VDD_CORE[9] VDD_CORE[8] VDD_CORE[7] VDD_CORE[6] VDD_CORE[5] VDD_CORE[4] VDD_CORE[3] VDD_CORE[2] VDD_CORE[1] VDD_CORE[0] EMPTY AJ18 AH18 AH17 AG19 AF18 VDD_095[4] VDD_095[3] VDD_095[2] VDD_095[1] VDD_095[0] V_3P3 AJ23 AF24 AJ25 AD28 AD26 AH24 AE27 AE25 AF28 AF26 AG27 AG25 AH28 AH26 AJ27 VDD_085 AJ13 V_FUSE EMPTY 1 C V_MEMCORE EMPTY AG16 AJ16 1 2 C3R22 1 UF 10% 6.3 V X5R 402 2 EMPTY C3T2 1 UF 10% 6.3 V X5R 402 1 VDD_33[1] VDD_33[0] C3T7 1 UF 10% 6.3 V X5R 402 2 VDDCR_MEM[9] VDDCR_MEM[8] VDDCR_MEM[7] VDDCR_MEM[6] VDDCR_MEM[5] VDDCR_MEM[4] VDDCR_MEM[3] VDDCR_MEM[2] VDDCR_MEM[1] VDDCR_MEM[0] AE21 AJ19 AF22 AF20 AG23 AG21 AD24 AH22 AH20 AE23 VDDBT_RTC_G AM25 VBURN[1] VBURN[0] AH12 AJ12 V_BAT EMPTY 1 C3T37 1 UF 10% 6.3 V X5R 402 2 AG15 AH15 AH14 AJ14 VDD_18[3] VDD_18[2] VDD_18[1] VDD_18[0] X862035-001 V_BURN EMPTY B BGA1443 1 V_SOC1P8VDD V_SOC1P8 EMPTY EMPTY 2 FB6D1 1 120 OHM 1.3 A 0.09DCR 1 1 C3R24 2 2 C7D3 4.7 UF 10% 6.3 V X5R 603 C3R21 1 UF 10% 6.3 V X5R 402 2 FB 402 1 2 C6D10 4.7 UF 10% 6.3 V X5R 603 1 UF 10% 6.3 V X5R 402 BGA1443 X862035-001 11 of 17 V_SOCPHY VDD_NB[14] VDD_NB[13] VDD_NB[12] VDD_NB[11] VDD_NB[10] VDD_NB[9] VDD_NB[8] VDD_NB[7] VDD_NB[6] VDD_NB[5] VDD_NB[4] VDD_NB[3] VDD_NB[2] VDD_NB[1] VDD_NB[0] BGA1443 A A MICROSOFT [PAGE_TITLE=SOC PAGE 2] 8 7 DRAWING Tue Jun 18 16:42:23 2013 CONFIDENTIAL 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 3/72 2 CSA PAGE 3/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 SOC POWER, V_GFXCORE + VSS D D V_GFXCORE EMPTY V_GFXCORE EMPTY V_GFXCORE EMPTY U7E1 C B U15 U13 U11 V23 V21 V19 V17 V15 V13 V11 W24 W22 W20 W18 W16 W14 W12 Y24 Y22 Y20 Y18 Y16 Y14 Y12 AA23 AA21 AA19 AA17 AA15 AA13 AA11 AB23 AB21 AB19 AB17 AB15 AB13 AB11 AC24 AC22 AC20 AC18 AC16 AC14 AC12 AD22 AD20 AD18 AD16 AD14 AD12 AE17 AE15 AE13 AE11 AF17 AF15 AF13 AF11 AG14 AG12 VDD_GFX[60] VDD_GFX[59] VDD_GFX[58] VDD_GFX[57] VDD_GFX[56] VDD_GFX[55] VDD_GFX[54] VDD_GFX[53] VDD_GFX[52] VDD_GFX[51] VDD_GFX[50] VDD_GFX[49] VDD_GFX[48] VDD_GFX[47] VDD_GFX[46] VDD_GFX[45] VDD_GFX[44] VDD_GFX[43] VDD_GFX[42] VDD_GFX[41] VDD_GFX[40] VDD_GFX[39] VDD_GFX[38] VDD_GFX[37] VDD_GFX[36] VDD_GFX[35] VDD_GFX[34] VDD_GFX[33] VDD_GFX[32] VDD_GFX[31] VDD_GFX[30] VDD_GFX[29] VDD_GFX[28] VDD_GFX[27] VDD_GFX[26] VDD_GFX[25] VDD_GFX[24] VDD_GFX[23] VDD_GFX[22] VDD_GFX[21] VDD_GFX[20] VDD_GFX[19] VDD_GFX[18] VDD_GFX[17] VDD_GFX[16] VDD_GFX[15] VDD_GFX[14] VDD_GFX[13] VDD_GFX[12] VDD_GFX[11] VDD_GFX[10] VDD_GFX[9] VDD_GFX[8] VDD_GFX[7] VDD_GFX[6] VDD_GFX[5] VDD_GFX[4] VDD_GFX[3] VDD_GFX[2] VDD_GFX[1] VDD_GFX[0] IC VDD_GFX 12 of 17 X862035-001 VDD_GFX[120] VDD_GFX[119] VDD_GFX[118] VDD_GFX[117] VDD_GFX[116] VDD_GFX[115] VDD_GFX[114] VDD_GFX[113] VDD_GFX[112] VDD_GFX[111] VDD_GFX[110] VDD_GFX[109] VDD_GFX[108] VDD_GFX[107] VDD_GFX[106] VDD_GFX[105] VDD_GFX[104] VDD_GFX[103] VDD_GFX[102] VDD_GFX[101] VDD_GFX[100] VDD_GFX[99] VDD_GFX[98] VDD_GFX[97] VDD_GFX[96] VDD_GFX[95] VDD_GFX[94] VDD_GFX[93] VDD_GFX[92] VDD_GFX[91] VDD_GFX[90] VDD_GFX[89] VDD_GFX[88] VDD_GFX[87] VDD_GFX[86] VDD_GFX[85] VDD_GFX[84] VDD_GFX[83] VDD_GFX[82] VDD_GFX[81] VDD_GFX[80] VDD_GFX[79] VDD_GFX[78] VDD_GFX[77] VDD_GFX[76] VDD_GFX[75] VDD_GFX[74] VDD_GFX[73] VDD_GFX[72] VDD_GFX[71] VDD_GFX[70] VDD_GFX[69] VDD_GFX[68] VDD_GFX[67] VDD_GFX[66] VDD_GFX[65] VDD_GFX[64] VDD_GFX[63] VDD_GFX[62] VDD_GFX[61] J23 J21 J19 J17 J15 J13 J11 K23 K21 K19 K17 K15 K13 K11 L24 L22 L20 L18 L16 L14 L12 M24 M22 M20 M18 M16 M14 M12 N23 N21 N19 N17 N15 N13 N11 P23 P21 P19 P17 P15 P13 P11 R24 R22 R20 R18 R16 R14 R12 T24 T22 T20 T18 T16 T14 T12 U23 U21 U19 U17 A23 A21 A19 A17 A15 A13 A11 A10 A9 B23 B21 B19 B17 B15 B13 B11 B10 C24 C22 C20 C18 C16 C14 C12 C10 D24 D22 D20 D18 D16 D14 D12 D10 E23 E21 E19 E17 E15 E13 E11 F23 F21 F19 F17 F15 F13 F11 G24 G22 G20 G18 G16 G14 G12 H24 H22 H20 H18 H16 H14 H12 BGA1443 VDD_GFX[181] VDD_GFX[180] VDD_GFX[179] VDD_GFX[178] VDD_GFX[177] VDD_GFX[176] VDD_GFX[175] VDD_GFX[174] VDD_GFX[173] VDD_GFX[172] VDD_GFX[171] VDD_GFX[170] VDD_GFX[169] VDD_GFX[168] VDD_GFX[167] VDD_GFX[166] VDD_GFX[165] VDD_GFX[164] VDD_GFX[163] VDD_GFX[162] VDD_GFX[161] VDD_GFX[160] VDD_GFX[159] VDD_GFX[158] VDD_GFX[157] VDD_GFX[156] VDD_GFX[155] VDD_GFX[154] VDD_GFX[153] VDD_GFX[152] VDD_GFX[151] VDD_GFX[150] VDD_GFX[149] VDD_GFX[148] VDD_GFX[147] VDD_GFX[146] VDD_GFX[145] VDD_GFX[144] VDD_GFX[143] VDD_GFX[142] VDD_GFX[141] VDD_GFX[140] VDD_GFX[139] VDD_GFX[138] VDD_GFX[137] VDD_GFX[136] VDD_GFX[135] VDD_GFX[134] VDD_GFX[133] VDD_GFX[132] VDD_GFX[131] VDD_GFX[130] VDD_GFX[129] VDD_GFX[128] VDD_GFX[127] VDD_GFX[126] VDD_GFX[125] VDD_GFX[124] VDD_GFX[123] VDD_GFX[122] VDD_GFX[121] VSS 14 of 17 AN30 AN26 AN23 AN20 AN17 AN14 AN12 AN9 AN5 AP36 AP35 AP31 AP25 AP22 AP19 AP16 AP13 AP8 AP4 AP3 AR37 AR27 AR24 AR21 AR18 AR15 AR2 AT36 AT32 AT28 AT26 AT23 AT20 AT17 AT14 AT11 AT7 AT3 AU38 AU37 AU33 AU29 AU25 AU22 AU19 AU16 AU13 AU10 AU6 AU2 AU1 AV38 AV37 AV27 AV24 AV21 AV18 AV15 AV12 AV2 AV1 VSS[60] VSS[59] VSS[58] VSS[57] VSS[56] VSS[55] VSS[54] VSS[53] VSS[52] VSS[51] VSS[50] VSS[49] VSS[48] VSS[47] VSS[46] VSS[45] VSS[44] VSS[43] VSS[42] VSS[41] VSS[40] VSS[39] VSS[38] VSS[37] VSS[36] VSS[35] VSS[34] VSS[33] VSS[32] VSS[31] VSS[30] VSS[29] VSS[28] VSS[27] VSS[26] VSS[25] VSS[24] VSS[23] VSS[22] VSS[21] VSS[20] VSS[19] VSS[18] VSS[17] VSS[16] VSS[15] VSS[14] VSS[13] VSS[12] VSS[11] VSS[10] VSS[9] VSS[8] VSS[7] VSS[6] VSS[5] VSS[4] VSS[3] VSS[2] VSS[1] VSS[0] VSS[120] VSS[119] VSS[118] VSS[117] VSS[116] VSS[115] VSS[114] VSS[113] VSS[112] VSS[111] VSS[110] VSS[109] VSS[108] VSS[107] VSS[106] VSS[105] VSS[104] VSS[103] VSS[102] VSS[101] VSS[100] VSS[99] VSS[98] VSS[97] VSS[96] VSS[95] VSS[94] VSS[93] VSS[92] VSS[91] VSS[90] VSS[89] VSS[88] VSS[87] VSS[86] VSS[85] VSS[84] VSS[83] VSS[82] VSS[81] VSS[80] VSS[79] VSS[78] VSS[77] VSS[76] VSS[75] VSS[74] VSS[73] VSS[72] VSS[71] VSS[70] VSS[69] VSS[68] VSS[67] VSS[66] VSS[65] VSS[64] VSS[63] VSS[62] VSS[61] MICROSOFT 5 4 VSS[240] VSS[239] VSS[238] VSS[237] VSS[236] VSS[235] VSS[234] VSS[233] VSS[232] VSS[231] VSS[230] VSS[229] VSS[228] VSS[227] VSS[226] VSS[225] VSS[224] VSS[223] VSS[222] VSS[221] VSS[220] VSS[219] VSS[218] VSS[217] VSS[216] VSS[215] VSS[214] VSS[213] VSS[212] VSS[211] VSS[210] VSS[209] VSS[208] VSS[207] VSS[206] VSS[205] VSS[204] VSS[203] VSS[202] VSS[201] VSS[200] VSS[199] VSS[198] VSS[197] VSS[196] VSS[195] VSS[194] VSS[193] VSS[192] VSS[191] VSS[190] VSS[189] VSS[188] VSS[187] VSS[186] VSS[185] VSS[184] VSS[183] VSS[182] VSS[181] U22 U20 U18 U16 U14 U12 U9 V36 V31 V28 V26 V24 V22 V20 V18 V16 V14 V12 V8 V3 W37 W34 W30 W27 W25 W23 W21 W19 W17 W15 W13 W11 W9 W5 W2 Y33 Y31 Y27 Y25 Y23 Y21 Y19 Y17 Y15 Y13 Y11 Y8 Y6 AA30 AA28 AA26 AA24 AA22 AA20 AA18 AA16 AA14 AA12 AA9 AB36 C B BGA1443 A BGA1443 DRAWING Tue Jun 18 16:42:24 2013 CONFIDENTIAL 6 VSS 15 of 17 VSS[180] VSS[179] VSS[178] VSS[177] VSS[176] VSS[175] VSS[174] VSS[173] VSS[172] VSS[171] VSS[170] VSS[169] VSS[168] VSS[167] VSS[166] VSS[165] VSS[164] VSS[163] VSS[162] VSS[161] VSS[160] VSS[159] VSS[158] VSS[157] VSS[156] VSS[155] VSS[154] VSS[153] VSS[152] VSS[151] VSS[150] VSS[149] VSS[148] VSS[147] VSS[146] VSS[145] VSS[144] VSS[143] VSS[142] VSS[141] VSS[140] VSS[139] VSS[138] VSS[137] VSS[136] VSS[135] VSS[134] VSS[133] VSS[132] VSS[131] VSS[130] VSS[129] VSS[128] VSS[127] VSS[126] VSS[125] VSS[124] VSS[123] VSS[122] VSS[121] X862035-001 [PAGE_TITLE=SOC PAGE 3] 7 AF8 AF3 AG37 AG34 AG30 AG28 AG26 AG24 AG22 AG20 AG18 AG9 AG5 AG2 AH33 AH31 AH27 AH25 AH23 AH21 AH19 AH16 AH13 AH8 AH6 AJ30 AJ26 AJ24 AJ20 AJ17 AJ15 AJ9 AK36 AK31 AK29 AK23 AK10 AK8 AK3 AL37 AL34 AL30 AL28 AL25 AL22 AL19 AL16 AL12 AL9 AL5 AL2 AM33 AM27 AM24 AM21 AM18 AM15 AM13 AM6 AN34 AB31 AB28 AB26 AB24 AB22 AB20 AB18 AB16 AB14 AB12 AB8 AB3 AC37 AC34 AC30 AC27 AC23 AC21 AC19 AC17 AC15 AC13 AC11 AC9 AC5 AC2 AD33 AD31 AD27 AD25 AD23 AD21 AD19 AD17 AD15 AD13 AD11 AD8 AD6 AE30 AE28 AE26 AE24 AE22 AE20 AE18 AE16 AE14 AE12 AE9 AF36 AF31 AF27 AF25 AF23 AF21 AF19 AF16 AF14 AF12 BGA1443 X862035-001 8 IC U7E1 VDD_GFX 13 of 17 X862035-001 A IC U7E1 IC U7E1 3 PROJECT NAME PAGE GREYBULL_RETAIL 4/72 2 CSA PAGE 4/72 1 FAB REV M 1.0 8 7 6 5 4 3 SOC, MEMORY PARTITION C + D U7E1 U7E1 D C B A 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 13 13 13 13 12 12 12 12 13 13 13 13 12 12 12 12 13 13 13 13 MD_DQ63 MD_DQ62 MD_DQ61 MD_DQ60 MD_DQ59 MD_DQ58 MD_DQ57 MD_DQ56 MD_DQ55 MD_DQ54 MD_DQ53 MD_DQ52 MD_DQ51 MD_DQ50 MD_DQ49 MD_DQ48 MD_DQ47 MD_DQ46 MD_DQ45 MD_DQ44 MD_DQ43 MD_DQ42 MD_DQ41 MD_DQ40 MD_DQ39 MD_DQ38 MD_DQ37 MD_DQ36 MD_DQ35 MD_DQ34 MD_DQ33 MD_DQ32 MD_DQ31 MD_DQ30 MD_DQ29 MD_DQ28 MD_DQ27 MD_DQ26 MD_DQ25 MD_DQ24 MD_DQ23 MD_DQ22 MD_DQ21 MD_DQ20 MD_DQ19 MD_DQ18 MD_DQ17 MD_DQ16 MD_DQ15 MD_DQ14 MD_DQ13 MD_DQ12 MD_DQ11 MD_DQ10 MD_DQ9 MD_DQ8 MD_DQ7 MD_DQ6 MD_DQ5 MD_DQ4 MD_DQ3 MD_DQ2 MD_DQ1 MD_DQ0 MD_DQSL_0_P MD_DQSL_0_N MD_DQSL_1_P MD_DQSL_1_N MD_DQSL_2_P MD_DQSL_2_N MD_DQSL_3_P MD_DQSL_3_N MD_DQSU_0_P MD_DQSU_0_N MD_DQSU_1_P MD_DQSU_1_N MD_DQSU_2_P MD_DQSU_2_N MD_DQSU_3_P MD_DQSU_3_N MD_DML_0 MD_DMU_0 MD_DML_1 MD_DMU_1 MD_DML_2 MD_DMU_2 MD_DML_3 MD_DMU_3 BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI P2 W1 N4 V2 N1 W3 P1 W4 Y2 M2 Y1 M1 T1 N3 U3 R4 M7 R6 M5 P7 M4 R8 N6 T4 L4 H1 L3 G4 L1 H2 K1 J1 H5 K5 H4 K4 G8 L6 H7 L8 G3 C1 G1 C3 F1 D2 E1 D1 C8 D5 E8 G6 D9 F5 B7 F4 A3 D6 B3 A7 D4 C6 C4 A6 B5 A5 E3 E4 J3 J4 R1 T2 E6 F7 J8 K7 P4 P5 U1 V1 A4 D7 F2 J6 K2 N8 U4 R3 IC MD_DQ63 MD_DQ62 MD_DQ61 MD_DQ60 MD_DQ59 MD_DQ58 MD_DQ57 MD_DQ56 MD_DQ55 MD_DQ54 MD_DQ53 MD_DQ52 MD_DQ51 MD_DQ50 MD_DQ49 MD_DQ48 MD_DQ47 MD_DQ46 MD_DQ45 MD_DQ44 MD_DQ43 MD_DQ42 MD_DQ41 MD_DQ40 MD_DQ39 MD_DQ38 MD_DQ37 MD_DQ36 MD_DQ35 MD_DQ34 MD_DQ33 MD_DQ32 MD_DQ31 MD_DQ30 MD_DQ29 MD_DQ28 MD_DQ27 MD_DQ26 MD_DQ25 MD_DQ24 MD_DQ23 MD_DQ22 MD_DQ21 MD_DQ20 MD_DQ19 MD_DQ18 MD_DQ17 MD_DQ16 MD_DQ15 MD_DQ14 MD_DQ13 MD_DQ12 MD_DQ11 MD_DQ10 MD_DQ9 MD_DQ8 MD_DQ7 MD_DQ6 MD_DQ5 MD_DQ4 MD_DQ3 MD_DQ2 MD_DQ1 MD_DQ0 MD_DQSL_0_P MD_DQSL_0_N MD_DQSL_1_P MD_DQSL_1_N MD_DQSL_2_P MD_DQSL_2_N MD_DQSL_3_P MD_DQSL_3_N MD_DQSU_0_P MD_DQSU_0_N MD_DQSU_1_P MD_DQSU_1_N MD_DQSU_2_P MD_DQSU_2_N MD_DQSU_3_P MD_DQSU_3_N MD_DML_0 MD_DMU_0 MD_DML_1 MD_DMU_1 MD_DML_2 MD_DMU_2 MD_DML_3 MD_DMU_3 MEM CHANNEL D 6 of 17 X862035-001 V_MEMIOCD EMPTY 1 MD_TEST AG11 40.2 OHM 1% 2 EMPTY 402 MD_TEST 1 MD_CLK0_DP MD_CLK0_DN K9 J10 MD_CLK0_DP MD_CLK0_DN MD_A15 MD_A14 MD_A13 MD_A12 MD_A11 MD_A10 MD_A9 MD_A8 MD_A7 MD_A6 MD_A5 MD_A4 MD_A3 MD_A2 MD_A1 MD_A0 V7 W10 U10 W6 Y5 N10 V9 W7 U7 Y7 V4 R10 U8 Y4 W8 T9 MD_A<15> MD_A<14> MD_A<13> MD_A<12> MD_A<11> MD_A<10> MD_A<9> MD_A<8> MD_A<7> MD_A<6> MD_A<5> MD_A<4> MD_A<3> MD_A<2> MD_A<1> MD_A<0> BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 MD_BA0 MD_BA1 MD_BA2 T7 V5 U6 MD_BA<0> MD_BA<1> MD_BA<2> BI BI BI 12 13 14 12 13 14 12 13 14 N7 L10 M9 R7 T5 P9 Y9 H9 F9 G10 MD_CKE0 MD_CAS_N MD_RAS_N MD_CS0_N MD_ODT0 MD_WE_N MD_RESET_N MD_CKE0 MD_CAS_N MD_RAS_N MD_CS0_N MD_ODT0 MD_WE_N MD_RESET MD_CKE1 MD_CS1_N MD_ODT1 MD_VREFDQ MD_ZVDDIO OUT OUT OUT OUT OUT OUT OUT OUT OUT 12 13 12 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 R3R13 40.2 OHM 1% 2 EMPTY 402 12 13 14 12 13 V_MEMIOCD 12 12 12 12 13 14 13 14 13 14 13 R2R5 MD_VREFDQ 1 2 MD_VREFDQ_MM MD_ZVDDIO 0 OHM 5% 402 EMPTY G7 J7 R3R14 EMPTY 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 16 16 16 16 15 15 15 15 16 16 16 14 16 15 15 15 15 16 1 R2R6 40.2 OHM 16 1% 16 2 CH 16 402 BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI MC_DQ63 MC_DQ62 MC_DQ61 MC_DQ60 MC_DQ59 MC_DQ58 MC_DQ57 MC_DQ56 MC_DQ55 MC_DQ54 MC_DQ53 MC_DQ52 MC_DQ51 MC_DQ50 MC_DQ49 MC_DQ48 MC_DQ47 MC_DQ46 MC_DQ45 MC_DQ44 MC_DQ43 MC_DQ42 MC_DQ41 MC_DQ40 MC_DQ39 MC_DQ38 MC_DQ37 MC_DQ36 MC_DQ35 MC_DQ34 MC_DQ33 MC_DQ32 MC_DQ31 MC_DQ30 MC_DQ29 MC_DQ28 MC_DQ27 MC_DQ26 MC_DQ25 MC_DQ24 MC_DQ23 MC_DQ22 MC_DQ21 MC_DQ20 MC_DQ19 MC_DQ18 MC_DQ17 MC_DQ16 MC_DQ15 MC_DQ14 MC_DQ13 MC_DQ12 MC_DQ11 MC_DQ10 MC_DQ9 MC_DQ8 MC_DQ7 MC_DQ6 MC_DQ5 MC_DQ4 MC_DQ3 MC_DQ2 MC_DQ1 MC_DQ0 MC_DQSL_0_P MC_DQSL_0_N MC_DQSL_1_P MC_DQSL_1_N MC_DQSL_2_P MC_DQSL_2_N MC_DQSL_3_P MC_DQSL_3_N MC_DQSU_0_P MC_DQSU_0_N MC_DQSU_1_P MC_DQSU_1_N MC_DQSU_2_P MC_DQSU_2_N MC_DQSU_3_P MC_DQSU_3_N MC_DML_0 MC_DMU_0 MC_DML_1 MC_DMU_1 MC_DML_2 MC_DMU_2 MC_DML_3 MC_DMU_3 7 X862035-001 BGA1443 6 MC_DQ63 MC_DQ62 MC_DQ61 MC_DQ60 MC_DQ59 MC_DQ58 MC_DQ57 MC_DQ56 MC_DQ55 MC_DQ54 MC_DQ53 MC_DQ52 MC_DQ51 MC_DQ50 MC_DQ49 MC_DQ48 MC_DQ47 MC_DQ46 MC_DQ45 MC_DQ44 MC_DQ43 MC_DQ42 MC_DQ41 MC_DQ40 MC_DQ39 MC_DQ38 MC_DQ37 MC_DQ36 MC_DQ35 MC_DQ34 MC_DQ33 MC_DQ32 MC_DQ31 MC_DQ30 MC_DQ29 MC_DQ28 MC_DQ27 MC_DQ26 MC_DQ25 MC_DQ24 MC_DQ23 MC_DQ22 MC_DQ21 MC_DQ20 MC_DQ19 MC_DQ18 MC_DQ17 MC_DQ16 MC_DQ15 MC_DQ14 MC_DQ13 MC_DQ12 MC_DQ11 MC_DQ10 MC_DQ9 MC_DQ8 MC_DQ7 MC_DQ6 MC_DQ5 MC_DQ4 MC_DQ3 MC_DQ2 MC_DQ1 MC_DQ0 MC_DQSL_0_P MC_DQSL_0_N MC_DQSL_1_P MC_DQSL_1_N MC_DQSL_2_P MC_DQSL_2_N MC_DQSL_3_P MC_DQSL_3_N MC_DQSU_0_P MC_DQSU_0_N MC_DQSU_1_P MC_DQSU_1_N MC_DQSU_2_P MC_DQSU_2_N MC_DQSU_3_P MC_DQSU_3_N MC_DML_0 MC_DMU_0 MC_DML_1 MC_DMU_1 MC_DML_2 MC_DMU_2 MC_DML_3 MC_DMU_3 5 4 1 IC MEM CHANNEL C 5 of 17 D C V_MEMIOCD EMPTY 1 R3R16 40.2 OHM 1% 2 EMPTY 402 MC_TEST AJ11 MC_TEST MC_CLK0_DP MC_CLK0_DN AK9 AJ10 MC_CLK0_DP MC_CLK0_DN MC_A15 MC_A14 MC_A13 MC_A12 MC_A11 MC_A10 MC_A9 MC_A8 MC_A7 MC_A6 MC_A5 MC_A4 MC_A3 MC_A2 MC_A1 MC_A0 AC8 AA7 AA10 AC6 AB4 AE10 AC7 AB9 AD9 AA8 AD5 AC10 AD7 AB5 AB7 AE7 MC_A<15> MC_A<14> MC_A<13> MC_A<12> MC_A<11> MC_A<10> MC_A<9> MC_A<8> MC_A<7> MC_A<6> MC_A<5> MC_A<4> MC_A<3> MC_A<2> MC_A<1> MC_A<0> BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 MC_BA0 MC_BA1 MC_BA2 AE8 AD4 AE6 MC_BA<0> MC_BA<1> MC_BA<2> BI BI BI 15 16 17 15 16 17 15 16 17 MC_CKE0 MC_CAS_N MC_RAS_N MC_CS0_N MC_ODT0 MC_WE_N MC_RESET MC_CKE1 MC_CS1_N MC_ODT1 AH9 AG10 AJ7 AF9 AF4 AG7 AA6 AH7 AF7 AG8 MC_CKE0 MC_CAS_N MC_RAS_N MC_CS0_N MC_ODT0 MC_WE_N MC_RESET_N MC_VREFDQ MC_ZVDDIO AL7 AL10 1 OUT OUT OUT OUT OUT OUT OUT OUT OUT 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 R3R15 40.2 OHM 1% 2 EMPTY 402 15 16 15 16 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 BGA1443 MICROSOFT DRAWING Tue Jun 18 16:42:18 2013 CONFIDENTIAL 16 16 16 16 16 16 3 MC_VREFDQ 1 2 MC_VREFDQ_MM MC_ZVDDIO 0 OHM 5% 402 EMPTY PROJECT NAME PAGE GREYBULL_RETAIL 5/72 2 B V_MEMIOCD 15 15 15 15 15 15 EMPTY 17 17 17 17 17 A 1 R3R5 40.2 OHM 1% 2 CH 402 R3R4 OUT [PAGE_TITLE=SOC MEMORY PARTITION A & B] 8 AN8 AM11 AM8 AN10 AR7 AP11 AP9 AR11 AV11 AR8 AU11 AV7 AV10 AT8 AR10 AV8 AT2 AN6 AP2 AN4 AT1 AM7 AN3 AP7 AU7 AV3 AV6 AU3 AT6 AR4 AV5 AT4 AJ8 AL6 AH4 AL8 AH5 AM5 AJ6 AM4 AR1 AK1 AP1 AJ4 AN1 AK2 AM1 AL1 AC1 AG4 AB2 AG3 AB1 AH1 AC3 AH2 AJ3 AA3 AJ1 AA1 AE3 AA4 AE4 AD1 AD2 AE1 AL3 AL4 AV4 AU5 AU9 AV9 AF2 AG1 AK4 AK5 AP5 AR5 AM9 AM10 AF1 AC4 AM2 AK7 AR6 AR3 AT10 AR9 2 OUT CSA PAGE 5/72 1 FAB REV M 1.0 8 7 D C B A BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI MB_DQ63 MB_DQ62 MB_DQ61 MB_DQ60 MB_DQ59 MB_DQ58 MB_DQ57 MB_DQ56 MB_DQ55 MB_DQ54 MB_DQ53 MB_DQ52 MB_DQ51 MB_DQ50 MB_DQ49 MB_DQ48 MB_DQ47 MB_DQ46 MB_DQ45 MB_DQ44 MB_DQ43 MB_DQ42 MB_DQ41 MB_DQ40 MB_DQ39 MB_DQ38 MB_DQ37 MB_DQ36 MB_DQ35 MB_DQ34 MB_DQ33 MB_DQ32 MB_DQ31 MB_DQ30 MB_DQ29 MB_DQ28 MB_DQ27 MB_DQ26 MB_DQ25 MB_DQ24 MB_DQ23 MB_DQ22 MB_DQ21 MB_DQ20 MB_DQ19 MB_DQ18 MB_DQ17 MB_DQ16 MB_DQ15 MB_DQ14 MB_DQ13 MB_DQ12 MB_DQ11 MB_DQ10 MB_DQ9 MB_DQ8 MB_DQ7 MB_DQ6 MB_DQ5 MB_DQ4 MB_DQ3 MB_DQ2 MB_DQ1 MB_DQ0 MB_DQSL_0_P MB_DQSL_0_N MB_DQSL_1_P MB_DQSL_1_N MB_DQSL_2_P MB_DQSL_2_N MB_DQSL_3_P MB_DQSL_3_N MB_DQSU_0_P MB_DQSU_0_N MB_DQSU_1_P MB_DQSU_1_N MB_DQSU_2_P MB_DQSU_2_N MB_DQSU_3_P MB_DQSU_3_N MB_DML_0 MB_DMU_0 MB_DML_1 MB_DMU_1 MB_DML_2 MB_DMU_2 MB_DML_3 MB_DMU_3 V37 N38 W38 P37 W36 N35 V38 N36 M37 Y38 M38 Y37 T38 W35 R35 U36 R33 M32 R31 N33 T35 M34 P32 M35 G35 L38 H37 L35 H38 L36 J35 K37 K34 H34 L33 H32 L31 H35 K35 G31 C36 G36 C38 G38 E35 F38 D38 E38 D34 C31 F34 B32 F35 E31 G33 D30 A32 B36 D33 A36 D35 A35 A33 C35 A34 B34 F37 E36 K38 J38 U38 T37 E33 D32 J31 J33 P35 P34 R38 P38 C33 F32 D37 K32 J36 N31 R36 U35 MB_DQ63 MB_DQ62 MB_DQ61 MB_DQ60 MB_DQ59 MB_DQ58 MB_DQ57 MB_DQ56 MB_DQ55 MB_DQ54 MB_DQ53 MB_DQ52 MB_DQ51 MB_DQ50 MB_DQ49 MB_DQ48 MB_DQ47 MB_DQ46 MB_DQ45 MB_DQ44 MB_DQ43 MB_DQ42 MB_DQ41 MB_DQ40 MB_DQ39 MB_DQ38 MB_DQ37 MB_DQ36 MB_DQ35 MB_DQ34 MB_DQ33 MB_DQ32 MB_DQ31 MB_DQ30 MB_DQ29 MB_DQ28 MB_DQ27 MB_DQ26 MB_DQ25 MB_DQ24 MB_DQ23 MB_DQ22 MB_DQ21 MB_DQ20 MB_DQ19 MB_DQ18 MB_DQ17 MB_DQ16 MB_DQ15 MB_DQ14 MB_DQ13 MB_DQ12 MB_DQ11 MB_DQ10 MB_DQ9 MB_DQ8 MB_DQ7 MB_DQ6 MB_DQ5 MB_DQ4 MB_DQ3 MB_DQ2 MB_DQ1 MB_DQ0 MB_DQSL_0_P MB_DQSL_0_N MB_DQSL_1_P MB_DQSL_1_N MB_DQSL_2_P MB_DQSL_2_N MB_DQSL_3_P MB_DQSL_3_N MB_DQSU_0_P MB_DQSU_0_N MB_DQSU_1_P MB_DQSU_1_N MB_DQSU_2_P MB_DQSU_2_N MB_DQSU_3_P MB_DQSU_3_N MB_DML_0 MB_DMU_0 MB_DML_1 MB_DMU_1 MB_DML_2 MB_DMU_2 MB_DML_3 MB_DMU_3 4 MEM CHANNEL B 7 of 17 V_MEMIOAB EMPTY 1 MB_TEST AJ28 R3T10 40.2 OHM 1% 2 EMPTY 402 MB_TEST 1 MB_CLK0_DP MB_CLK0_DN K30 J29 MB_CLK0_DP MB_CLK0_DN MB_A15 MB_A14 MB_A13 MB_A12 MB_A11 MB_A10 MB_A9 MB_A8 MB_A7 MB_A6 MB_A5 MB_A4 MB_A3 MB_A2 MB_A1 MB_A0 V32 W29 U29 W33 Y34 N29 V30 W32 U32 Y32 V35 R29 U31 Y35 W31 T30 MB_A<15> MB_A<14> MB_A<13> MB_A<12> MB_A<11> MB_A<10> MB_A<9> MB_A<8> MB_A<7> MB_A<6> MB_A<5> MB_A<4> MB_A<3> MB_A<2> MB_A<1> MB_A<0> BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 MB_BA0 MB_BA1 MB_BA2 T32 V34 U33 MB_BA<0> MB_BA<1> MB_BA<2> BI BI BI 18 19 20 18 19 20 18 19 20 MB_CKE0 MB_CAS_N MB_RAS_N MB_CS0_N MB_ODT0 MB_WE_N MB_RESET MB_CKE1 MB_CS1_N MB_ODT1 N32 L29 M30 R32 T34 P30 Y30 H30 F30 G29 MB_CKE0 MB_CAS_N MB_RAS_N MB_CS0_N MB_ODT0 MB_WE_N MB_RESET_N OUT OUT OUT OUT OUT OUT OUT OUT OUT 18 19 18 19 20 19 18 18 18 18 18 18 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 R3T13 40.2 OHM 1% 2 EMPTY 402 V_MEMIOAB 19 19 19 19 19 EMPTY 20 20 20 20 1 MB_VREFDQ MB_ZVDDIO MB_VREFDQ 1 2 MB_VREFDQ_MM MB_ZVDDIO 0 OHM 5% 402 EMPTY G32 J32 R2T1 40.2 OHM 1% 2 CH 402 R2T2 X862035-001 8 5 3 SOC, MEMORY PARTITION A + B IC U7E1 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 19 19 19 19 18 18 18 18 19 19 19 19 18 18 18 18 19 19 19 19 6 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 22 22 22 22 21 21 21 21 22 22 22 22 21 21 21 21 22 22 22 22 BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI MA_DQ63 MA_DQ62 MA_DQ61 MA_DQ60 MA_DQ59 MA_DQ58 MA_DQ57 MA_DQ56 MA_DQ55 MA_DQ54 MA_DQ53 MA_DQ52 MA_DQ51 MA_DQ50 MA_DQ49 MA_DQ48 MA_DQ47 MA_DQ46 MA_DQ45 MA_DQ44 MA_DQ43 MA_DQ42 MA_DQ41 MA_DQ40 MA_DQ39 MA_DQ38 MA_DQ37 MA_DQ36 MA_DQ35 MA_DQ34 MA_DQ33 MA_DQ32 MA_DQ31 MA_DQ30 MA_DQ29 MA_DQ28 MA_DQ27 MA_DQ26 MA_DQ25 MA_DQ24 MA_DQ23 MA_DQ22 MA_DQ21 MA_DQ20 MA_DQ19 MA_DQ18 MA_DQ17 MA_DQ16 MA_DQ15 MA_DQ14 MA_DQ13 MA_DQ12 MA_DQ11 MA_DQ10 MA_DQ9 MA_DQ8 MA_DQ7 MA_DQ6 MA_DQ5 MA_DQ4 MA_DQ3 MA_DQ2 MA_DQ1 MA_DQ0 MA_DQSL_0_P MA_DQSL_0_N MA_DQSL_1_P MA_DQSL_1_N MA_DQSL_2_P MA_DQSL_2_N MA_DQSL_3_P MA_DQSL_3_N MA_DQSU_0_P MA_DQSU_0_N MA_DQSU_1_P MA_DQSU_1_N MA_DQSU_2_P MA_DQSU_2_N MA_DQSU_3_P MA_DQSU_3_N MA_DML_0 MA_DMU_0 MA_DML_1 MA_DMU_1 MA_DML_2 MA_DMU_2 MA_DML_3 MA_DMU_3 AM28 AN31 AP28 AM30 AR28 AM31 AN29 AR32 AV32 AU28 AR31 AV28 AT31 AV29 AR29 AT29 AN33 AT37 AM32 AR36 AP32 AP37 AR34 AT38 AU36 AV33 AV36 AU32 AR35 AT33 AV35 AR33 AL33 AJ31 AM34 AJ33 AM35 AH35 AL31 AH34 AJ35 AP38 AK38 AR38 AK37 AM37 AM38 AN38 AG36 AB37 AG35 AC38 AH38 AB38 AG38 AA35 AA38 AJ38 AA36 AJ36 AE38 AH37 AD37 AF38 AE35 AE36 AL35 AL36 AV34 AU34 AU30 AV30 AC35 AC36 AK34 AK35 AN35 AN36 AR30 AP30 AD38 AF37 AL38 AK32 AT35 AP34 AV31 AM29 MA_DQ63 MA_DQ62 MA_DQ61 MA_DQ60 MA_DQ59 MA_DQ58 MA_DQ57 MA_DQ56 MA_DQ55 MA_DQ54 MA_DQ53 MA_DQ52 MA_DQ51 MA_DQ50 MA_DQ49 MA_DQ48 MA_DQ47 MA_DQ46 MA_DQ45 MA_DQ44 MA_DQ43 MA_DQ42 MA_DQ41 MA_DQ40 MA_DQ39 MA_DQ38 MA_DQ37 MA_DQ36 MA_DQ35 MA_DQ34 MA_DQ33 MA_DQ32 MA_DQ31 MA_DQ30 MA_DQ29 MA_DQ28 MA_DQ27 MA_DQ26 MA_DQ25 MA_DQ24 MA_DQ23 MA_DQ22 MA_DQ21 MA_DQ20 MA_DQ19 MA_DQ18 MA_DQ17 MA_DQ16 MA_DQ15 MA_DQ14 MA_DQ13 MA_DQ12 MA_DQ11 MA_DQ10 MA_DQ9 MA_DQ8 MA_DQ7 MA_DQ6 MA_DQ5 MA_DQ4 MA_DQ3 MA_DQ2 MA_DQ1 MA_DQ0 MA_DQSL_0_P MA_DQSL_0_N MA_DQSL_1_P MA_DQSL_1_N MA_DQSL_2_P MA_DQSL_2_N MA_DQSL_3_P MA_DQSL_3_N MA_DQSU_0_P MA_DQSU_0_N MA_DQSU_1_P MA_DQSU_1_N MA_DQSU_2_P MA_DQSU_2_N MA_DQSU_3_P MA_DQSU_3_N MA_DML_0 MA_DMU_0 MA_DML_1 MA_DMU_1 MA_DML_2 MA_DMU_2 MA_DML_3 MA_DMU_3 OUT X862035-001 MEM CHANNEL A 8 of 17 D C V_MEMIOAB EMPTY 1 AK28 MA_TEST MA_CLK0_DP MA_CLK0_DN AK30 AJ29 MA_CLK0_DP MA_CLK0_DN MA_A15 MA_A14 MA_A13 MA_A12 MA_A11 MA_A10 MA_A9 MA_A8 MA_A7 MA_A6 MA_A5 MA_A4 MA_A3 MA_A2 MA_A1 MA_A0 AC31 AA32 AA29 AC33 AB35 AE29 AC32 AB30 AD30 AA31 AD34 AC29 AD32 AB34 AB32 AE32 MA_A<15> MA_A<14> MA_A<13> MA_A<12> MA_A<11> MA_A<10> MA_A<9> MA_A<8> MA_A<7> MA_A<6> MA_A<5> MA_A<4> MA_A<3> MA_A<2> MA_A<1> MA_A<0> BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 MA_BA0 MA_BA1 MA_BA2 AE31 AD35 AE33 MA_BA<0> MA_BA<1> MA_BA<2> BI BI BI 21 22 23 21 22 23 21 22 23 MA_CKE0 MA_CAS_N MA_RAS_N MA_CS0_N MA_ODT0 MA_WE_N MA_RESET MA_CKE1 MA_CS1_N MA_ODT1 AH30 AG29 AJ32 AF30 AF35 AG32 AA33 AH32 AF32 AG31 MA_CKE0 MA_CAS_N MA_RAS_N MA_CS0_N MA_ODT0 MA_WE_N MA_RESET_N 1 MA_VREFDQ MA_ZVDDIO 5 4 R3T12 40.2 OHM 1% 2 EMPTY 402 MA_TEST OUT OUT OUT OUT OUT OUT OUT OUT OUT 21 22 21 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 23 23 22 21 21 22 21 22 21 22 21 22 21 22 21 22 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 R3T14 40.2 OHM 1% 2 EMPTY 402 EMPTY A 1 R3T17 40.2 OHM 1% 2 CH 402 R3T18 MA_VREFDQ_MM 1 2 AL32 MA_VREFDQ MA_ZVDDIO AL29 0 OHM 5% EMPTY 402 3 PROJECT NAME PAGE GREYBULL_RETAIL 6/72 2 B V_MEMIOAB 23 23 23 23 OUT BGA1443 MICROSOFT CONFIDENTIAL 6 1 IC U7E1 BGA1443 7 2 CSA PAGE 6/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 SOC VSS + SPARE D VSS/SPARE 16 of 17 M13 M11 M8 M6 N30 N28 N26 N24 N22 N20 N18 N16 N14 N12 N9 P36 P31 P28 P26 P24 P22 P20 P18 P16 P14 P12 P8 P3 R37 R34 R30 R27 R25 R23 R21 R19 R17 R15 R13 R11 R9 R5 R2 T33 T31 T27 T25 T23 T21 T19 T17 T15 T13 T11 T8 T6 U30 U28 U26 U24 C B D IC U7E1 IC U7E1 VSS[360] VSS[359] VSS[358] VSS[357] VSS[356] VSS[355] VSS[354] VSS[353] VSS[352] VSS[351] VSS[350] VSS[349] VSS[348] VSS[347] VSS[346] VSS[345] VSS[344] VSS[343] VSS[342] VSS[341] VSS[340] VSS[339] VSS[338] VSS[337] VSS[336] VSS[335] VSS[334] VSS[333] VSS[332] VSS[331] VSS[330] VSS[329] VSS[328] VSS[327] VSS[326] VSS[325] VSS[324] VSS[323] VSS[322] VSS[321] VSS[320] VSS[319] VSS[318] VSS[317] VSS[316] VSS[315] VSS[314] VSS[313] VSS[312] VSS[311] VSS[310] VSS[309] VSS[308] VSS[307] VSS[306] VSS[305] VSS[304] VSS[303] VSS[302] VSS[301] SPARE4 SPARE3 SPARE2 SPARE1 VSS[300] VSS[299] VSS[298] VSS[297] VSS[296] VSS[295] VSS[294] VSS[293] VSS[292] VSS[291] VSS[290] VSS[289] VSS[288] VSS[287] VSS[286] VSS[285] VSS[284] VSS[283] VSS[282] VSS[281] VSS[280] VSS[279] VSS[278] VSS[277] VSS[276] VSS[275] VSS[274] VSS[273] VSS[272] VSS[271] VSS[270] VSS[269] VSS[268] VSS[267] VSS[266] VSS[265] VSS[264] VSS[263] VSS[262] VSS[261] VSS[260] VSS[259] VSS[258] VSS[257] VSS[256] VSS[255] VSS[254] VSS[253] VSS[252] VSS[251] VSS[250] VSS[249] VSS[248] VSS[247] VSS[246] VSS[245] VSS[244] VSS[243] VSS[242] VSS[241] H31 H27 H25 H23 H21 H19 H17 H15 H13 H11 H8 H6 J30 J28 J26 J24 J22 J20 J18 J16 J14 J12 J9 K36 K31 K28 K26 K24 K22 K20 K18 K16 K14 K12 K8 K3 L37 L34 L30 L27 L25 L23 L21 L19 L17 L15 L13 L11 L9 L5 L2 M33 M31 M27 M25 M23 M21 M19 M17 M15 L7 L32 AG33 AG6 VSS 17 of 17 SOC_SPARE4 SOC_SPARE3 SOC_SPARE2 SOC_SPARE1 E26 E24 E22 E20 E18 E16 E14 E12 E9 E2 F36 F31 F28 F26 F24 F22 F20 F18 F16 F14 F12 F8 F3 G37 G34 G30 G27 G25 G23 G21 G19 G17 G15 G13 G11 G9 G5 G2 H33 EMPTY EMPTY 1 DB2R1 1 DB2T1 BI BI VSS[399] VSS[398] VSS[397] VSS[396] VSS[395] VSS[394] VSS[393] VSS[392] VSS[391] VSS[390] VSS[389] VSS[388] VSS[387] VSS[386] VSS[385] VSS[384] VSS[383] VSS[382] VSS[381] VSS[380] VSS[379] VSS[378] VSS[377] VSS[376] VSS[375] VSS[374] VSS[373] VSS[372] VSS[371] VSS[370] VSS[369] VSS[368] VSS[367] VSS[366] VSS[365] VSS[364] VSS[363] VSS[362] VSS[361] X862035-001 X862035-001 VSS[461] VSS[460] VSS[459] VSS[458] VSS[457] VSS[456] VSS[455] VSS[454] VSS[453] VSS[452] VSS[451] VSS[450] VSS[449] VSS[448] VSS[447] VSS[446] VSS[445] VSS[444] VSS[443] VSS[442] VSS[441] VSS[440] VSS[439] VSS[438] VSS[437] VSS[436] VSS[435] VSS[434] VSS[433] VSS[432] VSS[431] VSS[430] VSS[429] VSS[428] VSS[427] VSS[426] VSS[425] VSS[424] VSS[423] VSS[422] VSS[421] VSS[420] VSS[419] VSS[418] VSS[417] VSS[416] VSS[415] VSS[414] VSS[413] VSS[412] VSS[411] VSS[410] VSS[409] VSS[408] VSS[407] VSS[406] VSS[405] VSS[404] VSS[403] VSS[402] VSS[401] VSS[400] A38 A37 A28 A26 A24 A22 A20 A18 A16 A14 A12 A2 B38 B37 B35 B33 B28 B26 B24 B22 B20 B18 B16 B14 B12 B6 B4 B2 B1 C37 C34 C32 C29 C27 C25 C23 C21 C19 C17 C15 C13 C11 C7 C5 C2 D36 D31 D29 D27 D25 D23 D21 D19 D17 D15 D13 D11 D8 D3 E37 E30 E28 C B BGA1443 BGA1443 A A MICROSOFT [PAGE_TITLE=SOC PAGE 4] 8 7 DRAWING Tue Jun 18 16:42:24 2013 CONFIDENTIAL 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 7/72 2 CSA PAGE 7/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 SOC DEBUG + SB SIGNALS V_SOC1P8 1 D R4R22 10 KOHM 5% 2 CH 402 1 JTAG/DEBUG 4 of 17 R3R18 10 KOHM 5% 2 EMPTY 402 26 R3T8 IN X32K_X1 C R3T951 1 2 0 OHM 5% 402 EMPTY DB651 OUT A0_BYPASS SOC_THERMTRIP AN15 THERMTRIP* X32K_X2 X32K_X1_R AM23 AN24 X32K_X2 X32K_X1 GPIO_3P3_3 GPIO_3P3_2 GPIO_3P3_1 VREG_BURN_EN VREG_MEMCORE_VID1 VREG_MEMCORE_VID0 GPIO_1P8_1 GPIO_1P8_0 GPIO_POSTOUT_5 GPIO_POSTOUT_4 GPIO_POSTOUT_3 GPIO_POSTOUT_2 GPIO_POSTOUT_1 GPIO_POSTOUT_0 AK19 AN25 AK21 AK20 AL21 AL20 AM19 AM17 AM26 AR25 AP27 AP26 AR26 AT27 NEW_GPIO13 NEW_GPIO12 NEW_GPIO11 NEW_GPIO10 NEW_GPIO9 NEW_GPIO8 NEW_GPIO7 NEW_GPIO6 NEW_GPIO5 NEW_GPIO4 NEW_GPIO3 NEW_GPIO2 NEW_GPIO1 NEW_GPIO0 IN OUT IN IN OUT IN IN DBREQ_L DBRDY TRST_L TMS TDO TDI TCK AK26 AL26 AN27 AK24 AK25 AK22 AL23 DBREQ_N DBRDY TRST_N TMS TDO TDI TCK IN IN SOC_RST_N SOC_PWR_OK AR17 AR16 RESET_N PWROK BI BI BI BI BI BI IN IN OUT OUT OUT OUT IN IN BI BI BI SOC_TEST32_P SOC_TEST32_N SOC_TEST30_P SOC_TEST30_N SOC_TEST28_P SOC_TEST28_N TEST19 TEST18 TEST17 TEST16 TEST15 TEST14 TEST10 TEST9 SOC_TEST6 SOC_TEST5 SOC_TEST4 AL18 AK18 AK17 AL17 AL15 AK15 AJ21 AL27 AL11 AK13 AL14 AM16 AK12 AM14 AJ22 AK14 AL13 TEST32_P TEST32_N TEST30_P TEST30_N TEST28_P TEST28_N TEST19 TEST18 TEST17 TEST16 TEST15 TEST14 TEST10 TEST9 TEST6 TEST5 TEST4 DB3T4 70 68 70 68 R3T22 10 KOHM 5% 2 CH 402 OUT BI BI BI BI BI BI BI R3T21 BI 1 AK16 OUT 1 B A0_BYPASS 51 68 26 26 V_SOC1P8 10 KOHM 5% 2 EMPTY 402 ATE_TSTCLK_EN DLY_PSP_RESET 58 68 68 68 68 68 68 68 1 AK11 AL24 BI BI BI BI 1 1 0 OHM 5% 2 CH 402 29 ATE_TSTCLK_EN BI R3T7 1 2 0 OHM 5% 402 EMPTY D IC U7E1 TMON_CAL1 TMON_CAL0 AM22 AM20 PSEN AG13 TMON_CAL1 TMON_CAL0 BI BI C V_SOC1P8 1 R5T13 10 KOHM 5% 2 CH 402 ALERT_N AN16 SP_SMC_INT_N OUT 26 SVT SVD SVC SID SIC RTCCLK E10 C9 F10 AP18 AP17 AK27 SVT SVD SVC SID SIC RTCCLK IN BI OUT 44 44 44 M_VREF AH11 M_VREF VDDCR_MEM_SENSE VDD_MEM0_SENSE VDD_MEM1_SENSE VSS_GFX_SENSE VDD_GFX_SENSE AE19 AF5 AF34 B8 B9 SOC_MEMCORE_S SOC_MEMIOAB_S SOC_MEMIOCD_S SOC_GFXCPU_S_RTN SOC_GFXCORE_S VDD_NB_SENSE AC25 SOC_NBCORE_S BI VDD_CORE_SENSE VDD_095_SENSE A8 AG17 SOC_CPUCORE_S OUT X862035-001 R3T4 R3T2 BI IN BI BI BI OUT OUT SB_SOC_DATA 2 1 1% 243 OHM CH 402 SB_SOC_CLK 2 1 1% 243 OHM CH 402 8 8 44 8 45 26 BI IN 26 B V_SOCPHY 8 44 BGA1443 V_MEMIOCD EMPTY R3R3 1 KOHM 1% 2 CH 402 M_VREF 1 R3R2 1 KOHM 1 C3R20 1% 1 UF 10% 2 CH 6.3 V 402 2 X5R V_CPUCORE EMPTYV_GFXCORE 1 A OUT 8 8 8 8 IN IN IN EMPTY SOC_CPUCORE_S EMPTY 1 DB2R6 SOC_GFXCORE_S EMPTY 1 DB2R2 SOC_GFXCPU_S_RTN 1 DB2R3 EMPTY EMPTY EMPTY 1 DB1T2 EMPTY 1 DB2R4 1 DB2R5 A 402 MICROSOFT [PAGE_TITLE=SOC PAGE 4] 8 7 DRAWING Tue Jun 18 16:42:29 2013 CONFIDENTIAL 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 8/72 2 CSA PAGE 8/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 SOC, DECOUPLING 42 0805 22UF V_GFXCORE EMPTY D EMPTY 1 C2T17 2 1 22 UF 20% 6.3 V X7R 805 1 C2T39 C2T32 2 1 1 C2R33 2 1 C2T10 2 1 B C2R23 1 2 1 C2R38 C2T11 C2R16 2 1 C8D5 2 C2R10 2 22 UF 20% 6.3 V X7R 805 1 2 C2T14 2 22 UF 20% 6.3 V X7R 805 2 1 C2T34 2 22 UF 20% 6.3 V X7R 805 1 2 C2R35 2 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 2 1 C2T12 2 1 C2R20 2 22 UF 20% 6.3 V X7R 805 1 C2R21 1 C2R39 1 C2T15 C2R37 C2R36 1 C2R13 2 1 C8D3 2 1 22 UF 20% 6.3 V X7R 805 1 C2R12 C2T38 2 1 C2R18 2 1 1 C2R19 1 2 2 C8D6 2 C8E2 2 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 C2R22 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 2 2 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 1 1 1 C2R40 2 22 UF 20% 6.3 V X7R 805 1 1 1 1 C2T35 C2R11 1 C2R17 C2T16 1 7 C2T1 2 C3T3 2 C3R18 2 C3R17 2 10 UF 10% 6.3 V X5R 805 1 C2R28 1 C2T21 1 2 C2T26 2 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 1 C2T9 2 1 C2R27 2 1 C2T20 1 2 C2T25 2 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 1 C2T8 1 2 C2T40 2 1 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 1 C2R26 2 1 C2R25 C2T19 2 1 10 UF 10% 6.3 V X5R 805 1 2 C2T18 C2T44 2 C 10 UF 10% 6.3 V X5R 805 1 2 C2T42 2 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 1 C2T24 1 2 C3T4 2 1 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 1 C2R24 2 1 C2T5 C2T45 1 2 1 C2T43 C2T27 2 2 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 2 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 1 C2R32 2 1 C2T6 2 1 B C2T31 2 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 1 C2R31 2 1 C2T7 2 1 C2T30 2 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 1 C2T41 2 10 UF 10% 6.3 V X5R 805 1 C2R30 2 1 C2T23 2 1 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 C2T29 2 10 UF 10% 6.3 V X5R 805 2 1 C2R29 1 2 C2T22 2 1 10 UF 10% 6.3 V X5R 805 10 UF 10% 6.3 V X5R 805 C2T28 2 A 10 UF 10% 6.3 V X5R 805 2 22 UF 20% 6.3 V X7R 805 MICROSOFT DRAWING CONFIDENTIAL Tue Jun 18 16:42:26 2013 6 2 2 [PAGE_TITLE=GCPU, DECOUPLING] 8 2 2 22 UF 20% 6.3 V X7R 805 1 2 10 UF 10% 6.3 V X5R 805 22 UF 20% 6.3 V X7R 805 1 C3R16 2 22 UF 20% 6.3 V X7R 805 1 C2T2 10 UF 10% 6.3 V X5R 805 22 UF 20% 6.3 V X7R 805 1 2 10 UF 10% 6.3 V X5R 805 2 C2T37 22 UF 20% 6.3 V X7R 805 1 2 C2T13 2 C2T3 10 UF 10% 6.3 V X5R 805 C2R9 1 2 10 UF 10% 6.3 V X5R 805 2 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 1 22 UF 20% 6.3 V X7R 805 1 C2T4 10 UF 10% 6.3 V X5R 805 22 UF 20% 6.3 V X7R 805 1 2 2 22 UF 20% 6.3 V X7R 805 2 1 22 UF 20% 6.3 V X7R 805 C2T33 C3R19 10 UF 10% 6.3 V X5R 805 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 1 1 2 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 A 2 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 1 C2R34 C2T36 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 1 1 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 C 2 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 1 C8E3 D 44 0805 10UF V_GFXCORE 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 9/72 2 CSA PAGE 9/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 SOC, DECOUPLING V_CPUCORE EMPTY 10 0805 22UF 13 0805 10UF V_NBCORE V_SOCPHY EMPTY EMPTY D V_MEMCORE D EMPTY 1 2 C3T33 1 10% 10 UF 6.3 V X5R 805 2 C2T68 1 10% 10 UF 6.3 V X5R 805 C2T61 2 1 10 UF 10% 6.3 V X5R 805 1 C2T60 2 1 22 UF 20% 6.3 V X7R 805 C2T67 C8E9 2 22 UF 20% 6.3 V X7R 805 2 1 10 UF 10% 6.3 V X5R 805 C C8E7 2 22 UF 20% 6.3 V X7R 805 1 10 UF 10% 6.3 V X5R 805 C2T59 C2T66 C2T51 1 1 2 1 1 1 C2T58 2 1 10 UF 10% 6.3 V X5R 805 1 C2T57 C2T56 2 1 1 C2T55 C2T49 1 2 2 1 C2T63 1 2 1 2 C3T12 1 2 1 C3T11 1 2 C2T47 1 2 C2T71 C3T30 C3T28 C3T25 1 C3T26 1 C2T54 2 1 10 UF 10% 6.3 V X5R 805 1 C2T53 C3T34 2 1 1 A C2T52 1 2 1 C2T50 I75 1 C2T48 2 1 1 2 1 C3T31 1 2 2 2 2 1 C3T32 2 1 C4U8 C5F14 1 C5F13 2 1 C6F10 1 C6F8 1 1 1 2 1 1 C2T70 2 22 UF 20% 6.3 V X7R 805 C3T23 2 C3T20 2 C3T22 1 C5T2 2 22 UF 20% 6.3 V X7R 805 1 C5T1 2 22 UF 20% 6.3 V X7R 805 1 C4T20 C 2 22 UF 20% 6.3 V X7R 805 1 C4T19 2 22 UF 20% 6.3 V X7R 805 2 C3T5 2 B C3T1 2 22 UF 20% 4 V X5R 603 2 1 C3T56 2 22 UF 20% 4 V X5R 603 2 22 UF 20% 6.3 V EMPTY 805 1 C3T57 2 22 UF 20% 4 V X5R 603 2 1 C3T6 2 22 UF 20% 4 V X5R 603 22 UF 20% 6.3 V X7R 805 I73 C5T3 22 UF 20% 4 V X5R 603 10 UF 10% 6.3 V X5R 805 2 1 4.7 UF 20% 6.3 V X5R 402 2 22 UF 20% 6.3 V EMPTY 805 C6F7 2 4.7 UF 20% 6.3 V X5R 402 2 22 UF 20% 6.3 V EMPTY 805 1 C3T53 4.7 UF 20% 6.3 V X5R 402 2 22 UF 20% 6.3 V EMPTY 805 1 2 4.7 UF 20% 6.3 V X5R 402 22 UF 20% 6.3 V EMPTY 805 1 UF 10% 6.3 V X5R 402 2 C5U7 C3T19 4.7 UF 20% 6.3 V X5R 402 22 UF 20% 6.3 V X7R 805 2 C3T35 1 22 UF 20% 6.3 V X7R 805 2 C3T24 C4U7 2 2 22 UF 20% 6.3 V X7R 805 1 UF 10% 6.3 V X5R 402 22 UF 20% 6.3 V X7R 805 2 22 UF 20% 6.3 V X7R 805 C2T72 1 1 UF 10% 6.3 V X5R 402 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 2 10 UF 10% 6.3 V X5R 805 1 2 22 UF 20% 6.3 V X7R 805 10 UF 10% 6.3 V X5R 805 1 C2T65 2 C3T36 C4U6 C3T21 4.7 UF 20% 6.3 V X5R 402 22 UF 20% 6.3 V X7R 805 2 1 1 1 1 UF 10% 6.3 V X5R 402 22 UF 20% 6.3 V X7R 805 C2T46 2 1 UF 10% 6.3 V X5R 402 2 2 1 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 2 C3T29 C5U8 22 UF 20% 6.3 V X7R 805 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 2 1 1 UF 10% 6.3 V X5R 402 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 10 UF 10% 6.3 V X5R 805 1 2 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 C2T64 C8E6 C3T16 2 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 10 UF 10% 6.3 V X5R 805 B 1 2 22 UF 20% 6.3 V X7R 805 10 UF 10% 6.3 V X5R 805 1 C2T62 1 2 2 1 C8E4 C3T15 C3T27 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 1 2 1 UF 10% 6.3 V X5R 402 22 UF 20% 6.3 V X7R 805 C2T80 C3T8 A 2 22 UF 20% 6.3 V X7R 805 1 C2T73 2 22 UF 20% 6.3 V X7R 805 MICROSOFT CONFIDENTIAL [PAGE_TITLE=GCPU, DECOUPLING] 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 10/72 2 CSA PAGE 10/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 SOC, DECOUPLING D D V_MEMIOCD V_MEMIOAB EMPTY V_MEMIOCD EMPTY EMPTY 1 C3R7 2 0.22 UF 10% 6.3 V X5R 402 1 C2R4 2 0.22 UF 10% 6.3 V X5R 402 1 C C3R10 2 0.22 UF 10% 6.3 V X5R 402 1 C3R9 2 0.22 UF 10% 6.3 V X5R 402 1 C3R8 2 0.22 UF 10% 6.3 V X5R 402 1 C3R11 2 0.22 UF 10% 6.3 V X5R 402 B 1 C3R12 2 0.22 UF 10% 6.3 V X5R 402 1 C2R3 2 0.22 UF 10% 6.3 V X5R 402 1 C2R5 2 0.22 UF 10% 6.3 V X5R 402 1 C2R6 2 0.22 UF 10% 6.3 V X5R 402 EMPTY V_MEMIOAB 1 C2R7 2 0.22 UF 10% 6.3 V X5R 402 1 C3R5 C3R14 2 0.22 UF 10% 6.3 V X5R 402 1 C3R6 2 0.22 UF 10% 6.3 V X5R 402 1 C2R8 C3R4 1 2 1 1 C2R1 1 C2R2 C3R15 1 2 1 10 UF 20% 6.3 V X5R 805 1 C2R15 1 1 C2R14 0.22 UF 10% 6.3 V X5R 402 1 C3R13 1 EMPTY 2 0.22 UF 10% 6.3 V X5R 402 2 C3T42 2 C3T41 2 C2R42 C2R41 1 C3R28 C3T39 2 C2T79 2 0.22 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 1 2 0.22 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 1 C2T69 0.22 UF 10% 6.3 V X5R 402 1 1 1 C2T76 2 0.22 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 1 A C3R27 1 C2T74 2 0.22 UF 10% 6.3 V X5R 402 1 C2T77 C3T46 10 UF 20% 6.3 V X5R 805 2 1 1 2 0.22 UF 10% 6.3 V X5R 402 1 C2T78 1 C3T48 1 2 C3T52 C 2 10 UF 20% 6.3 V X5R 805 1 2 0.22 UF 10% 6.3 V X5R 402 C2T82 10 UF 20% 6.3 V X5R 805 0.22 UF 10% 6.3 V X5R 402 C3T45 2 2 0.22 UF 10% 6.3 V X5R 402 1 C2T81 C3T51 2 10 UF 20% 6.3 V X5R 805 2 0.22 UF 10% 6.3 V X5R 402 1 C3T44 2 B V_MEMIOAB EMPTY V_MEMIOCD 2 2 C3T50 0.22 UF 10% 6.3 V X5R 402 2 0.22 UF 10% 6.3 V X5R 402 2 0.22 UF 10% 6.3 V X5R 402 2 0.22 UF 10% 6.3 V X5R 402 C3T49 0.22 UF 10% 6.3 V X5R 402 0.22 UF 10% 6.3 V X5R 402 1 2 0.22 UF 10% 6.3 V X5R 402 2 10 UF 20% 6.3 V X5R 805 1 C3T40 0.22 UF 10% 6.3 V X5R 402 2 10 UF 20% 6.3 V X5R 805 1 2 1 10 UF 20% 6.3 V X5R 805 C3R2 C3T38 0.22 UF 10% 6.3 V X5R 402 2 0.22 UF 10% 6.3 V X5R 402 1 C3R3 2 0.22 UF 10% 6.3 V X5R 402 1 1 0.22 UF 10% 6.3 V X5R 402 1 C2T75 2 0.22 UF 10% 6.3 V X5R 402 1 C3T47 2 0.22 UF 10% 6.3 V X5R 402 1 C3T43 2 0.22 UF 10% 6.3 V X5R 402 1 C3T54 2 1 UF 10% 6.3 V X5R 402 1 C2T83 2 1 UF 10% 6.3 V X5R 402 1 C2T84 2 1 UF 10% 6.3 V X5R 402 1 C3T55 2 2 A 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 MICROSOFT CONFIDENTIAL [PAGE_TITLE=GCPU, DECOUPLING] 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 11/72 2 CSA PAGE 11/72 1 FAB REV M 1.0 8 7 6 4 3 EMPTY U9C1 MEM DDR3_4GBIT_X16 BYTE LANE 0 BYTE LANE 1 EMPTY BYTE LANE 2 BYTE LANE 3 V_MEMIOCD EMPTY R8C23 1 KOHM 1% 2 CH 402 MD_VREFCAA 1 R8C24 1 KOHM 1 C8C12 1% 1 UF 10% 2 CH 6.3 V 402 2 X5R R9 R1 N9 N1 K8 K2 G7 D9 B2 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 H9 H2 F1 E9 D2 C9 C1 A8 A1 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 X866978-001 MS_PART# U9C1,U8C5 MATL EMPTY NC4 NC3 NC2 NC1 L9 L1 J9 J1 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 T9 T1 P9 P1 M9 M1 J8 J2 G8 E1 B3 A9 VSSQ9 VSSQ8 VSSQ7 VSSQ6 VSSQ5 VSSQ4 VSSQ3 VSSQ2 VSSQ1 G9 G1 F9 E8 E2 D8 D1 B9 B1 EMPTY U8C5 MEM DDR3_4GBIT_X16 V_MEMIOCD R8C20 1 KOHM 1% 2 CH 402MD_VREFCAB 1 1 R8C19 C8C11 1 KOHM 1 UF 1% 10% 6.3 V 2 CH 2 X5R 402 402 OUT 12 V_MEMIOCD 1 OUT R8C38 1 KOHM 1% 2 CH 402 MD_VREFDQB 12 R8C37 1 KOHM 1% 2 CH 402 1 1 2 402 MEMORY 12 EMPTY R9C47 1 KOHM 1% 2 CH 402 MD_VREFDQA 1 R9C46 1 KOHM 1 C1P14 1% 1 UF 10% 2 CH 6.3 V 402 2 X5R 1 TRUEDESCR. DUMMY_BOM OUT V_MEMIOCD EMPTY BGA96 D EMPTY 1 402 REF_DES 1 V_MEMIOCD 1 C 2 MEMORY CHANNEL D V_MEMIOCD D 5 OUT 12 R9 R1 N9 N1 K8 K2 G7 D9 B2 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 H9 H2 F1 E9 D2 C9 C1 A8 A1 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 C2P16 1 UF 10% 6.3 V X5R 402 X866978-001 NC4 NC3 NC2 NC1 L9 L1 J9 J1 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 T9 T1 P9 P1 M9 M1 J8 J2 G8 E1 B3 A9 VSSQ9 VSSQ8 VSSQ7 VSSQ6 VSSQ5 VSSQ4 VSSQ3 VSSQ2 VSSQ1 G9 G1 F9 E8 E2 D8 D1 B9 B1 C BGA96 BOM PROPERTY MD_CLK_TERM_RC R1P22 1 U9C1 DDR3_4GBIT_X16 5 5 5 5 B 5 5 A BI BI BI BI IN IN MD_DQSU_0_P MD_DQSU_0_N MD_DQSL_0_P MD_DQSL_0_N MD_RESET_N MD_A<15..0> C7 B7 F3 G3 T2 DQSU_P DQSU_N DQSL_P DQSL_N RESET_N 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M7 T7 T3 N7 R7 L7 R3 T8 R2 R8 P2 P8 N2 P3 P7 N3 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 0 M3 N8 M2 BA2 BA1 BA0 5 IN MD_BA<2..0> 5 5 5 5 5 IN IN IN IN IN MD_WE_N MD_CAS_N MD_RAS_N MD_DMU_0 MD_DML_0 L3 K3 J3 D3 E7 WE_N CAS_N RAS_N DMU DML IN IN MD_VREFCAA MD_VREFDQA M8 H1 VREFCA VREFDQ 12 12 X866978-001 36.5 OHM 1% CH 2 MEM 402 CK_P CK_N J7 K7 1 R1P23 1 36.5 OHM 1% CH 2 402 MD_CLK0_DP MD_CLK0_DN C1P19 0.1 UF 10% 6.3 V X5R 402 2 5 5 DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0 A3 B8 A2 A7 C2 C8 C3 D7 MD_DQ15 MD_DQ14 MD_DQ13 MD_DQ12 MD_DQ11 MD_DQ10 MD_DQ9 MD_DQ8 BI BI BI BI BI BI BI BI 5 5 5 5 5 5 5 5 DQL7 DQL6 DQL5 DQL4 DQL3 DQL2 DQL1 DQL0 H7 G2 H8 H3 F8 F2 F7 E3 MD_DQ7 MD_DQ6 MD_DQ5 MD_DQ4 MD_DQ3 MD_DQ2 MD_DQ1 MD_DQ0 BI BI BI BI BI BI BI BI 5 5 5 5 5 5 5 5 CKE CS_N K9 L2 MD_CKE0 MD_CS0_N IN IN 5 5 ODT ZQ K1 L8 MD_ODT0 MD_ZQ0 IN 5 BGA96 5 5 5 5 5 5 IN IN 1 U8C5 MEM DDR3_4GBIT_X16 MD_DQSU_1_P MD_DQSU_1_N MD_DQSL_1_P MD_DQSL_1_N MD_RESET_N MD_A<15..0> C7 B7 F3 G3 T2 DQSU_P DQSU_N DQSL_P DQSL_N RESET_N 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M7 T7 T3 N7 R7 L7 R3 T8 R2 R8 P2 P8 N2 P3 P7 N3 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 0 M3 N8 M2 BA2 BA1 BA0 5 IN MD_BA<2..0> 5 5 5 5 5 IN IN IN IN IN MD_WE_N MD_CAS_N MD_RAS_N MD_DMU_1 MD_DML_1 L3 K3 J3 D3 E7 WE_N CAS_N RAS_N DMU DML IN IN MD_VREFCAB MD_VREFDQB M8 H1 VREFCA VREFDQ 12 12 R8C29 BI BI BI BI IN IN 243 OHM 1% 2 CH 402 X866978-001 MICROSOFT DRAWING Tue Jun 18 16:42:22 2013 CONFIDENTIAL [PAGE_TITLE=MEMORY PARTITION A, LOW] 8 7 6 5 4 3 CK_P CK_N J7 K7 MD_CLK0_DP MD_CLK0_DN IN IN DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0 A3 B8 A2 A7 C2 C8 C3 D7 MD_DQ31 MD_DQ30 MD_DQ29 MD_DQ28 MD_DQ27 MD_DQ26 MD_DQ25 MD_DQ24 BI BI BI BI BI BI BI BI 5 5 5 5 5 5 5 5 DQL7 DQL6 DQL5 DQL4 DQL3 DQL2 DQL1 DQL0 H7 G2 H8 H3 F8 F2 F7 E3 MD_DQ23 MD_DQ22 MD_DQ21 MD_DQ20 MD_DQ19 MD_DQ18 MD_DQ17 MD_DQ16 BI BI BI BI BI BI BI BI 5 5 5 5 5 5 5 5 CKE CS_N K9 L2 MD_CKE0 MD_CS0_N IN IN 5 5 ODT ZQ K1 L8 MD_ODT0 MD_ZQ1 IN R8C28 5 1 B A 243 OHM 1% 2 CH 402 BGA96 PROJECT NAME PAGE GREYBULL_RETAIL 12/72 2 5 5 CSA PAGE 12/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 MEMORY CHANNEL D V_MEMIOCD BYTE LANE 4 BYTE LANE 5 EMPTY MEM U8C4 DDR3_4GBIT_X16 D BYTE LANE 6 BYTE LANE 7 V_MEMIOCD EMPTY V_MEMIOCD VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 H9 H2 F1 E9 D2 C9 C1 A8 A1 C VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 X866978-001 NC4 NC3 NC2 NC1 L9 L1 J9 J1 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 T9 T1 P9 P1 M9 M1 J8 J2 G8 E1 B3 A9 VSSQ9 VSSQ8 VSSQ7 VSSQ6 VSSQ5 VSSQ4 VSSQ3 VSSQ2 VSSQ1 G9 G1 F9 E8 E2 D8 D1 B9 B1 R8C16 1 KOHM 1% 2 CH 402 1 EMPTY R7C5 1 KOHM 1% 2 CH 402 MD_VREFCAD OUT 13 R7C4 1 KOHM 1% 2 CH 402 1 1 2 C8C10 1 UF 10% 6.3 V X5R 402 1 2 13 OUT C7C6 1 UF 10% 6.3 V X5R 402 V_MEMIOCD EMPTY V_MEMIOCD EMPTY R8C34 1 KOHM 1% 2 CH 402 MD_VREFDQD 1 R8C33 1 C2P14 1 KOHM 1 UF 1% 10% 2 CH 6.3 V 2 X5R 402 402 1 R8C36 1 KOHM 1% 2 CH 402 MD_VREFDQC 1 R8C35 1 KOHM 1 C2P15 1% 1 UF 10% 2 CH 6.3 V 402 2 X5R 1 BGA96 OUT 13 OUT 13 R9 R1 N9 N1 K8 K2 G7 D9 B2 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 H9 H2 F1 E9 D2 C9 C1 A8 A1 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 402 MS_PART# U8C4,U8C3 MATL EMPTY REF_DES EMPTY TRUEDESCR. DUMMY_BOM MEMORY X866978-001 B 5 5 5 5 5 5 5 5 A 13 13 BI BI BI BI IN IN MD_DQSU_2_P MD_DQSU_2_N MD_DQSL_2_P MD_DQSL_2_N MD_RESET_N MD_A<15..0> C7 B7 F3 G3 T2 DQSU_P DQSU_N DQSL_P DQSL_N RESET_N 12 11 10 9 8 7 6 5 4 3 2 1 0 M7 T7 T3 N7 R7 L7 R3 T8 R2 R8 P2 P8 N2 P3 P7 N3 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 0 M3 N8 M2 BA2 BA1 BA0 L3 K3 J3 D3 E7 WE_N CAS_N RAS_N DMU DML M8 H1 VREFCA VREFDQ 15 14 13 IN MD_BA<2..0> IN IN IN IN IN MD_WE_N MD_CAS_N MD_RAS_N MD_DMU_2 MD_DML_2 IN IN MD_VREFCAC MD_VREFDQC X866978-001 7 L9 L1 J9 J1 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 T9 T1 P9 P1 M9 M1 J8 J2 G8 E1 B3 A9 VSSQ9 VSSQ8 VSSQ7 VSSQ6 VSSQ5 VSSQ4 VSSQ3 VSSQ2 VSSQ1 G9 G1 F9 E8 E2 D8 D1 B9 B1 C BGA96 CK_P CK_N MEM U8C3 DDR3_4GBIT_X16 J7 K7 MD_CLK0_DP MD_CLK0_DN IN IN 5 5 DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0 A3 B8 A2 A7 C2 C8 C3 D7 MD_DQ47 MD_DQ46 MD_DQ45 MD_DQ44 MD_DQ43 MD_DQ42 MD_DQ41 MD_DQ40 BI BI BI BI BI BI BI BI 5 5 5 5 5 5 5 5 DQL7 DQL6 DQL5 DQL4 DQL3 DQL2 DQL1 DQL0 H7 G2 H8 H3 F8 F2 F7 E3 MD_DQ39 MD_DQ38 MD_DQ37 MD_DQ36 MD_DQ35 MD_DQ34 MD_DQ33 MD_DQ32 BI BI BI BI BI BI BI BI 5 5 5 5 5 5 5 5 CKE CS_N K9 L2 MD_CKE0 MD_CS0_N IN IN 5 5 ODT ZQ K1 L8 MD_ODT0 MD_ZQ2 IN 5 1 BGA96 5 5 5 5 5 5 5 5 5 5 5 5 13 13 R8C27 6 BI BI BI BI IN IN MD_DQSU_3_P MD_DQSU_3_N MD_DQSL_3_P MD_DQSL_3_N MD_RESET_N MD_A<15..0> C7 B7 F3 G3 T2 DQSU_P DQSU_N DQSL_P DQSL_N RESET_N 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M7 T7 T3 N7 R7 L7 R3 T8 R2 R8 P2 P8 N2 P3 P7 N3 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 0 M3 N8 M2 BA2 BA1 BA0 IN MD_BA<2..0> IN IN IN IN IN MD_WE_N MD_CAS_N MD_RAS_N MD_DMU_3 MD_DML_3 L3 K3 J3 D3 E7 WE_N CAS_N RAS_N DMU DML IN IN MD_VREFCAD MD_VREFDQD M8 H1 VREFCA VREFDQ 243 OHM 1% 2 CH 402 X866978-001 MICROSOFT DRAWING Tue Jun 18 16:42:22 2013 CONFIDENTIAL [PAGE_TITLE=MEMORY PARTITION A, HIGH] 8 NC4 NC3 NC2 NC1 BOM PROPERTY MEM U8C4 DDR3_4GBIT_X16 5 5 5 5 D MEM U8C3 DDR3_4GBIT_X16 1 R8C17 1 KOHM 1% 2 CH 402 MD_VREFCAC 1 R9 R1 N9 N1 K8 K2 G7 D9 B2 V_MEMIOCD EMPTY 5 4 3 CK_P CK_N J7 K7 MD_CLK0_DP MD_CLK0_DN IN IN DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0 A3 B8 A2 A7 C2 C8 C3 D7 MD_DQ63 MD_DQ62 MD_DQ61 MD_DQ60 MD_DQ59 MD_DQ58 MD_DQ57 MD_DQ56 BI BI BI BI BI BI BI BI 5 5 5 5 5 5 5 5 DQL7 DQL6 DQL5 DQL4 DQL3 DQL2 DQL1 DQL0 H7 G2 H8 H3 F8 F2 F7 E3 MD_DQ55 MD_DQ54 MD_DQ53 MD_DQ52 MD_DQ51 MD_DQ50 MD_DQ49 MD_DQ48 BI BI BI BI BI BI BI BI 5 5 5 5 5 5 5 5 CKE CS_N K9 L2 MD_CKE0 MD_CS0_N IN IN 5 5 ODT ZQ K1 L8 MD_ODT0 MD_ZQ3 IN 5 1 B A R7C7 243 OHM 1% 2 CH 402 BGA96 PROJECT NAME PAGE GREYBULL_RETAIL 13/72 2 5 5 CSA PAGE 13/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 MEMORY CHANNEL D, DECOUPLING + TERMINATION PARTITION D DECOUPLING D D V_MEMIOCD V_VTTD 1 5 IN MD_A<15..0> IN MD_WE_N 5 IN MD_CAS_N 1 2 36.5 OHM 1% CH 402 5 IN MD_RAS_N 1 2 36.5 OHM1% CH 402 5 IN MD_ODT0 5 IN MD_CKE0 R9C7 15 1 2 36.5 OHM1% CH 402 14 1 2 36.5 OHM1% CH 402 13 1 2 36.5 OHM1% CH 402 R1P4 C 12 11 R9C6 1 2 36.5 OHM1% CH 402 MD_CS0_N 1 2 36.5 OHM1% CH 402 1 R1P15 1 2 36.5 OHM 1% CH 402 2 R1P12 2 2 C8C9 22 UF 20% 6.3 V X7R 805 C1P13 1 C1P18 1 C1P5 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 1 C2P3 1 UF 10% 6.3 V X5R 402 2 1 C1P11 1 C1P17 1 C1P12 1 C1P16 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 C 1 2 36.5 OHM 1% CH 402 V_MEMIOCD MEMORY D, CHIP 1 DECOUPLING V_VTTD R1P6 R9C9 1 2 5 1 2 36.5 OHM1% CH 402 R9C16 IN MD_BA<2..0> 2 1 1 2 36.5 OHM1% CH 402 R8C26 R1P13 2 C2P22 1 C2P11 1 C2P26 1 C2P4 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 1 1 UF 10% 6.3 V X5R 402 C2P18 1 C2P9 1 C2P20 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 I499 B R8C25 1 2 36.5 OHM 1% CH 402 V_MEMIOCD R9C27 MEMORY D, CHIP 2, DECOUPLING 1 2 36.5 OHM1% CH 402 1 R9C10 2 0 1 C2P8 1 UF 10% 6.3 V X5R 402 1 2 36.5 OHM 1% CH 402 1 2 36.5 OHM 1% CH 402 R1P7 1 2 36.5 OHM1% CH 402 C2P24 1 C2P25 1 C2P7 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 1 2 C2P5 1 UF 10% 6.3 V X5R 402 1 2 C2P10 1 C2P19 1 C2P13 1 C2P17 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 R9C25 3 1 2 36.5 OHM1% CH 402 2 1 2 36.5 OHM1% CH 402 R9C8 V_MEMIOCD MEMORY D, CHIP 3, DECOUPLING R9C5 1 2 36.5 OHM1% CH 402 1 R9C12 2 1 2 36.5 OHM1% CH 402 7 6 5 C3P6 1 UF 10% 6.3 V X5R 402 1 2 C2P12 1 C2P23 1 C2P21 1 C3P13 1 C3P15 1 C2P6 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 MICROSOFT [PAGE_TITLE=MEMORY PARTITION A, DECOUPLING, TERMINATION] 8 22 UF 20% 6.3 V X7R 805 MEMORY D, CHIP 0, DECOUPLING 1 2 36.5 OHM 1% CH 402 5 0 1 C8C8 V_MEMIOCD R9C34 1 2 36.5 OHM1% CH 402 1 2 1 R1P16 6 4 22 UF 20% 6.3 V X7R 805 R9C31 R9C15 9 7 IN 2 1 2 36.5 OHM1% CH 402 1 2 36.5 OHM1% CH 402 B 5 1 2 36.5 OHM1% CH 402 C9C22 R9C11 10 8 A R1P5 22 UF 20% 6.3 V X7R 805 R1P14 5 1 C7C4 V_VTTD 1 UF 10% 6.3 V X5R 402 DRAWING Tue Jun 18 16:42:22 2013 CONFIDENTIAL 4 3 2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 1 2 C3P1 1 UF 10% 6.3 V X5R 402 PROJECT NAME PAGE GREYBULL_RETAIL 14/72 2 A CSA PAGE 14/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 MEMORY CHANNEL C V_MEMIOCD BYTE LANE 0 BYTE LANE 1 MEM U7C2 DDR3_4GBIT_X16 D BYTE LANE 2 BYTE LANE 3 V_MEMIOCD R7C2 1 KOHM 1% 2 CH 402 MC_VREFCAA V_MEMIOCD 1 C R9 R1 N9 N1 K8 K2 G7 D9 B2 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 H9 H2 F1 E9 D2 C9 C1 A8 A1 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 NC4 NC3 NC2 NC1 MATL EMPTY R7C1 1 KOHM 1% 2 CH 402 1 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 T9 T1 P9 P1 M9 M1 J8 J2 G8 E1 B3 A9 VSSQ9 VSSQ8 VSSQ7 VSSQ6 VSSQ5 VSSQ4 VSSQ3 VSSQ2 VSSQ1 G9 G1 F9 E8 E2 D8 D1 B9 B1 OUT C7C5 1 UF 10% 6.3 V X5R 402 BGA96 EMPTY V_MEMIOCD 5 5 5 5 5 5 15 15 BI BI BI BI IN IN R7C11 1 KOHM 1% 2 CH 402 MC_VREFDQB 1 1 R7C10 C3P9 1 KOHM 1 UF 1% 10% 6.3 V 2 CH 2 X5R 402 402 1 15 402 TRUEDESCR. DUMMY_BOM MEMORY MC_DQSU_0_P MC_DQSU_0_N MC_DQSL_0_P MC_DQSL_0_N MC_RESET_N MC_A<15..0> DQSU_P DQSU_N DQSL_P DQSL_N RESET_N 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M7 T7 T3 N7 R7 L7 R3 T8 R2 R8 P2 P8 N2 P3 P7 N3 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 0 M3 N8 M2 BA2 BA1 BA0 MC_BA<2..0> IN IN IN IN IN MC_WE_N MC_CAS_N MC_RAS_N MC_DMU_0 MC_DML_0 L3 K3 J3 D3 E7 WE_N CAS_N RAS_N DMU DML IN IN MC_VREFCAA MC_VREFDQA M8 H1 VREFCA VREFDQ R4R6 1 36.5 OHM 1% CH 2 MEM 402 CK_P CK_N J7 K7 1 R4R7 1 36.5 OHM 1% CH 2 402 2 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 H9 H2 F1 E9 D2 C9 C1 A8 A1 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 15 X866978-001 NC4 NC3 NC2 NC1 L9 L1 J9 J1 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 T9 T1 P9 P1 M9 M1 J8 J2 G8 E1 B3 A9 VSSQ9 VSSQ8 VSSQ7 VSSQ6 VSSQ5 VSSQ4 VSSQ3 VSSQ2 VSSQ1 G9 G1 F9 E8 E2 D8 D1 B9 B1 C BGA96 C4R21 0.1 UF 10% 6.3 V X5R 402 MC_CLK0_DP MC_CLK0_DN IN IN MEM U7C1 DDR3_4GBIT_X16 5 5 A3 B8 A2 A7 C2 C8 C3 D7 MC_DQ15 MC_DQ14 MC_DQ13 MC_DQ12 MC_DQ11 MC_DQ10 MC_DQ9 MC_DQ8 BI BI BI BI BI BI BI BI 5 5 5 5 5 5 5 5 DQL7 DQL6 DQL5 DQL4 DQL3 DQL2 DQL1 DQL0 H7 G2 H8 H3 F8 F2 F7 E3 MC_DQ7 MC_DQ6 MC_DQ5 MC_DQ4 MC_DQ3 MC_DQ2 MC_DQ1 MC_DQ0 BI BI BI BI BI BI BI BI 5 5 5 5 5 5 5 5 CKE CS_N K9 L2 MC_CKE0 MC_CS0_N IN IN 5 5 ODT ZQ K1 L8 MC_ODT0 MC_ZQ0 IN 5 BGA96 5 5 5 5 5 5 DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0 1 5 5 5 5 5 5 15 15 R7C8 6 BI BI BI BI IN IN MC_DQSU_1_P MC_DQSU_1_N MC_DQSL_1_P MC_DQSL_1_N MC_RESET_N MC_A<15..0> C7 B7 F3 G3 T2 DQSU_P DQSU_N DQSL_P DQSL_N RESET_N 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M7 T7 T3 N7 R7 L7 R3 T8 R2 R8 P2 P8 N2 P3 P7 N3 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 0 M3 N8 M2 BA2 BA1 BA0 IN MC_BA<2..0> IN IN IN IN IN MC_WE_N MC_CAS_N MC_RAS_N MC_DMU_1 MC_DML_1 L3 K3 J3 D3 E7 WE_N CAS_N RAS_N DMU DML IN IN MC_VREFCAB MC_VREFDQB M8 H1 VREFCA VREFDQ 243 OHM 1% 2 CH 402 MICROSOFT DRAWING Tue Jun 18 16:42:23 CONFIDENTIAL 2013 5 4 3 CK_P CK_N J7 K7 MC_CLK0_DP MC_CLK0_DN IN IN DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0 A3 B8 A2 A7 C2 C8 C3 D7 MC_DQ31 MC_DQ30 MC_DQ29 MC_DQ28 MC_DQ27 MC_DQ26 MC_DQ25 MC_DQ24 BI BI BI BI BI BI BI BI 5 5 5 5 5 5 5 5 DQL7 DQL6 DQL5 DQL4 DQL3 DQL2 DQL1 DQL0 H7 G2 H8 H3 F8 F2 F7 E3 MC_DQ23 MC_DQ22 MC_DQ21 MC_DQ20 MC_DQ19 MC_DQ18 MC_DQ17 MC_DQ16 BI BI BI BI BI BI BI BI 5 5 5 5 5 5 5 5 CKE CS_N K9 L2 MC_CKE0 MC_CS0_N IN IN 5 5 ODT ZQ K1 L8 MC_ODT0 MC_ZQ1 IN 5 1 X866978-001 [PAGE_TITLE=MEMORY PARTITION B, LOW] 7 OUT R9 R1 N9 N1 K8 K2 G7 D9 B2 MC_CLK_TERM_RC X866978-001 8 D BOM PROPERTY C7 B7 F3 G3 T2 IN 15 402 R7C14 1 KOHM 1% 2 CH 402 MC_VREFDQA OUT 1 R7C13 1 KOHM 1 C3P10 1% 1 UF 10% 2 CH 6.3 V 402 2 X5R REF_DES 5 5 5 5 5 5 A 2 15 V_MEMIOCD U7C2 DDR3_4GBIT_X16 B 1 R6C6 1 KOHM 1% 2 CH 402 MC_VREFCAB OUT 1 R6C5 1 KOHM 1 C6C3 1% 1 UF 10% 2 CH 6.3 V 402 2 X5R 1 1 X866978-001 MS_PART# U7C2,U7C1 L9 L1 J9 J1 MEM U7C1 DDR3_4GBIT_X16 V_MEMIOCD B A R6C12 243 OHM 1% 2 CH 402 BGA96 PROJECT NAME PAGE GREYBULL_RETAIL 15/72 2 5 5 CSA PAGE 15/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 MEMORY CHANNEL C D BYTE LANE 4 BYTE LANE 5 V_MEMIOCD MEM U6D2 DDR3_4GBIT_X16 BYTE LANE 6 BYTE LANE 7 V_MEMIOCD V_MEMIOCD R6D35 1 KOHM 1% 2 CH 402 MC_VREFCAD 1 R6D13 1 KOHM 1% 2 CH 402 MC_VREFCAC 1 C R9 R1 N9 N1 K8 K2 G7 D9 B2 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 H9 H2 F1 E9 D2 C9 C1 A8 A1 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 X866978-001 NC4 NC3 NC2 NC1 L9 L1 J9 J1 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 T9 T1 P9 P1 M9 M1 J8 J2 G8 E1 B3 A9 VSSQ9 VSSQ8 VSSQ7 VSSQ6 VSSQ5 VSSQ4 VSSQ3 VSSQ2 VSSQ1 G9 G1 F9 E8 E2 D8 D1 B9 B1 OUT 16 R6D36 1 KOHM 1% 2 CH 402 1 R6D14 1 KOHM 1% 2 CH 402 1 1 2 C6D8 1 UF 10% 6.3 V X5R 402 2 OUT 16 C4R29 1 UF 10% 6.3 V X5R 402 V_MEMIOCD V_MEMIOCD R6D20 1 KOHM 1% 2 CH 402 MC_VREFDQD OUT 1 R6D22 1 C4R14 1 KOHM 1 UF 1% 10% 6.3 V 2 CH 2 X5R 402 402 1 R6D5 1 KOHM 1% 2 CH 402 MC_VREFDQC 1 R6D6 1 KOHM 1 C4R1 1% 1 UF 10% 2 CH 6.3 V 402 2 X5R 1 BGA96 1 OUT 16 D V_MEMIOCD U6D3 MEM DDR3_4GBIT_X16 R9 R1 N9 N1 K8 K2 G7 D9 B2 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 H9 H2 F1 E9 D2 C9 C1 A8 A1 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 16 X866978-001 NC4 NC3 NC2 NC1 L9 L1 J9 J1 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 T9 T1 P9 P1 M9 M1 J8 J2 G8 E1 B3 A9 VSSQ9 VSSQ8 VSSQ7 VSSQ6 VSSQ5 VSSQ4 VSSQ3 VSSQ2 VSSQ1 G9 G1 F9 E8 E2 D8 D1 B9 B1 C BGA96 402 MS_PART# U6D2,U6D3 MATL EMPTY REF_DES EMPTY TRUEDESCR. DUMMY_BOM MEMORY BOM PROPERTY MEM U6D2 DDR3_4GBIT_X16 5 5 5 5 5 B 5 A BI BI BI BI IN IN MC_DQSU_2_P MC_DQSU_2_N MC_DQSL_2_P MC_DQSL_2_N MC_RESET_N MC_A<15..0> 5 IN MC_BA<2..0> 5 5 5 5 5 IN IN IN IN IN MC_WE_N MC_CAS_N MC_RAS_N MC_DMU_2 MC_DML_2 IN IN MC_VREFCAC MC_VREFDQC 16 16 C7 B7 F3 G3 T2 DQSU_P DQSU_N DQSL_P DQSL_N RESET_N 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M7 T7 T3 N7 R7 L7 R3 T8 R2 R8 P2 P8 N2 P3 P7 N3 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 0 M3 N8 M2 BA2 BA1 BA0 L3 K3 J3 D3 E7 WE_N CAS_N RAS_N DMU DML M8 H1 CK_P CK_N VREFCA VREFDQ X866978-001 MEM U6D3 DDR3_4GBIT_X16 J7 K7 MC_CLK0_DP MC_CLK0_DN IN IN 5 5 DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0 A3 B8 A2 A7 C2 C8 C3 D7 MC_DQ47 MC_DQ46 MC_DQ45 MC_DQ44 MC_DQ43 MC_DQ42 MC_DQ41 MC_DQ40 BI BI BI BI BI BI BI BI 5 5 5 5 5 5 5 5 DQL7 DQL6 DQL5 DQL4 DQL3 DQL2 DQL1 DQL0 H7 G2 H8 H3 F8 F2 F7 E3 MC_DQ39 MC_DQ38 MC_DQ37 MC_DQ36 MC_DQ35 MC_DQ34 MC_DQ33 MC_DQ32 BI BI BI BI BI BI BI BI 5 5 5 5 5 5 5 5 CKE CS_N K9 L2 MC_CKE0 MC_CS0_N ODT ZQ K1 L8 MC_ODT0 MC_ZQ2 1 BGA96 5 5 5 5 5 5 IN IN 5 5 IN 5 5 5 5 5 5 5 16 16 R6D17 243 OHM 1% 2 CH 402 7 6 MC_DQSU_3_P MC_DQSU_3_N MC_DQSL_3_P MC_DQSL_3_N MC_RESET_N MC_A<15..0> IN MC_BA<2..0> IN IN IN IN IN MC_WE_N MC_CAS_N MC_RAS_N MC_DMU_3 MC_DML_3 IN IN MC_VREFCAD MC_VREFDQD C7 B7 F3 G3 T2 DQSU_P DQSU_N DQSL_P DQSL_N RESET_N 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M7 T7 T3 N7 R7 L7 R3 T8 R2 R8 P2 P8 N2 P3 P7 N3 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 0 M3 N8 M2 BA2 BA1 BA0 L3 K3 J3 D3 E7 WE_N CAS_N RAS_N DMU DML M8 H1 VREFCA VREFDQ X866978-001 MICROSOFT CONFIDENTIAL [PAGE_TITLE=MEMORY PARTITION B, HIGH] 8 BI BI BI BI IN IN 5 4 DRAWING Tue Jun 18 16:42:23 2013 3 CK_P CK_N J7 K7 MC_CLK0_DP MC_CLK0_DN IN IN DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0 A3 B8 A2 A7 C2 C8 C3 D7 MC_DQ63 MC_DQ62 MC_DQ61 MC_DQ60 MC_DQ59 MC_DQ58 MC_DQ57 MC_DQ56 BI BI BI BI BI BI BI BI 5 5 5 5 5 5 5 5 DQL7 DQL6 DQL5 DQL4 DQL3 DQL2 DQL1 DQL0 H7 G2 H8 H3 F8 F2 F7 E3 MC_DQ55 MC_DQ54 MC_DQ53 MC_DQ52 MC_DQ51 MC_DQ50 MC_DQ49 MC_DQ48 BI BI BI BI BI BI BI BI 5 5 5 5 5 5 5 5 CKE CS_N K9 L2 MC_CKE0 MC_CS0_N IN IN 5 5 ODT ZQ K1 L8 MC_ODT0 MC_ZQ3 IN 5 1 A R6D37 243 OHM 1% 2 CH 402 BGA96 PROJECT NAME PAGE GREYBULL_RETAIL 16/72 2 B 5 5 CSA PAGE 16/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 MEMORY CHANNEL C, DECOUPLING + TERMINATION V_VTTC D PARTITION C DECOUPLING D V_MEMIOCD V_VTTC 5 5 IN IN MC_A<15..0> R4R13 15 1 2 36.5 OHM1% CH 402 14 1 2 36.5 OHM1% CH 402 13 1 2 36.5 OHM1% CH 402 5 IN MC_CAS_N 5 IN MC_RAS_N 5 IN MC_ODT0 5 IN MC_CKE0 5 IN MC_CS0_N R4R8 12 C MC_WE_N 11 10 9 8 7 6 B 5 4 3 2 1 0 R4R9 R6D28 1 2 36.5 OHM1% CH 402 R4R10 1 2 36.5 OHM1% CH 402 R6D27 1 2 36.5 OHM1% CH 402 R6D31 1 2 36.5 OHM 1% CH 402 1 R4R17 2 1 2 36.5 OHM1% CH 402 C6D7 1 22 UF 20% 6.3 V X7R 805 2 2 1 C7C2 22 UF 20% 6.3 V X7R 805 2 C4R30 22 UF 20% 6.3 V X7R 805 R4R18 1 2 36.5 OHM 1% CH 402 R6D16 1 2 36.5 OHM1% CH 402 V_MEMIOCD MEMORY C, CHIP 0 DECOUPLING R4R16 1 2 36.5 OHM1% CH 402 1 R4R12 1 2 36.5 OHM1% CH 402 2 5 IN MC_BA<2..0> 2 1 2 36.5 OHM1% CH 402 1 C3P8 1 UF 10% 6.3 V X5R 402 2 C3P12 1 UF 10% 6.3 V X5R 402 1 C3P2 1 UF 10% 6.3 V X5R 402 2 1 2 C3P17 1 UF 10% 6.3 V X5R 402 1 C3P14 1 UF 10% 6.3 V X5R 402 2 1 C3P5 1 UF 10% 6.3 V X5R 402 2 1 C3P19 1 UF 10% 6.3 V X5R 402 2 1 2 C3P4 C 1 UF 10% 6.3 V X5R 402 R6D23 1 1 2 36.5 OHM1% CH 402 R6D32 0 1 2 36.5 OHM1% CH 402 V_MEMIOCD R4R14 MEMORY C, CHIP 1, DECOUPLING 1 2 36.5 OHM 1% CH 402 1 R6D33 1 2 36.5 OHM1% CH 402 1 C4P2 1 UF 10% 6.3 V X5R 402 2 R6D19 2 C3P3 1 1 UF 10% 6.3 V X5R 402 2 1 C4P5 1 UF 10% 6.3 V X5R 402 2 1 C3P7 1 UF 10% 6.3 V X5R 402 2 1 C3P11 1 UF 10% 6.3 V X5R 402 2 1 C4P4 1 UF 10% 6.3 V X5R 402 C3P18 1 C3P16 1 UF 10% 6.3 V X5R 402 2 2 1 UF 10% 6.3 V X5R 402 1 2 36.5 OHM 1% CH 402 B R6D21 1 2 36.5 OHM1% CH 402 V_MEMIOCD R6D30 MEMORY C, CHIP 2, DECOUPLING 1 2 36.5 OHM1% CH 402 1 R4R11 1 2 36.5 OHM1% CH 402 2 R6D25 C4R8 1 UF 10% 6.3 V X5R 402 1 2 C4R10 1 C4R7 1 2 2 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 C4R3 1 UF 10% 6.3 V X5R 402 1 2 C4R11 1 C4R5 1 2 2 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 1 C4R4 1 UF 10% 6.3 V X5R 402 2 C4R2 1 UF 10% 6.3 V X5R 402 1 2 36.5 OHM1% CH 402 R6D29 1 2 36.5 OHM1% CH 402 R6D26 V_MEMIOCD 1 2 36.5 OHM1% CH 402 MEMORY C, CHIP 3, DECOUPLING 1 A 2 7 6 5 C4R23 1 UF 10% 6.3 V X5R 402 1 2 C4R17 1 UF 10% 6.3 V X5R 402 1 2 C4R16 1 C4R27 1 2 2 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 C4R25 1 UF 10% 6.3 V X5R 402 MICROSOFT [PAGE_TITLE=MEMORY PARTITION B, DECOUPLING, TERMINATION] 8 1 C7C3 22 UF 20% 6.3 V X7R 805 V_VTTC R6D24 1 2 36.5 OHM1% CH 402 R4R15 1 2 DRAWING Tue Jun 18 16:42:23 2013 CONFIDENTIAL 4 3 C4R18 1 UF 10% 6.3 V X5R 402 1 2 C4R19 1 UF 10% 6.3 V X5R 402 1 2 C4R24 PROJECT NAME PAGE GREYBULL_RETAIL 17/72 2 A 1 UF 10% 6.3 V X5R 402 CSA PAGE 17/72 1 FAB REV M 1.0 8 7 6 I37 MEM U9F5 DDR3_4GBIT_X16 R9 R1 N9 N1 K8 K2 G7 D9 B2 H9 H2 F1 E9 D2 C9 C1 A8 A1 NC4 NC3 NC2 NC1 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 C X866978-001 T9 T1 P9 P1 M9 M1 J8 J2 G8 E1 B3 A9 VSSQ9 VSSQ8 VSSQ7 VSSQ6 VSSQ5 VSSQ4 VSSQ3 VSSQ2 VSSQ1 G9 G1 F9 E8 E2 D8 D1 B9 B1 V_MEMIOAB BYTE LANE 0 BYTE LANE 1 L9 L1 J9 J1 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 4 3 2 1 MEMORY CHANNEL B V_MEMIOAB D 5 R9F21 1 KOHM 1% 2 CH 402 MB_VREFCAA 1 R9F20 1 KOHM 1% 2 CH 402 1 1 OUT R8F20 1 KOHM 1% 2 CH 402 MB_VREFCAB 18 R8F21 1 KOHM 1% 2 CH 402 C9F15 1 V_MEMIOAB 1 BGA96 1 2 OUT 18 C8F4 1 UF 10% 6.3 V X5R 402 V_MEMIOAB R8F6 1 KOHM 1% 2 CH 402 MB_VREFDQA 1 R8F7 1 KOHM 1 C2U13 1% 1 UF 10% 2 CH 6.3 V 402 2 X5R R8F3 1 KOHM 1% 2 CH 402MB_VREFDQB OUT 1 R8F4 1 C2U12 1 KOHM 1 UF 1% 10% 6.3 V 2 CH 2 X5R 402 402 1 OUT I111 MEM U8F3 DDR3_4GBIT_X16 1 1 UF 10% 6.3 V X5R 402 2 V_MEMIOAB V_MEMIOAB BYTE LANE 2 BYTE LANE 3 18 402 18 R9 R1 N9 N1 K8 K2 G7 D9 B2 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 H9 H2 F1 E9 D2 C9 C1 A8 A1 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 X866978-001 MS_PART# U9F5,U8F3 MATL EMPTY REF_DES EMPTY TRUEDESCR. DUMMY_BOM MEMORY D NC4 NC3 NC2 NC1 L9 L1 J9 J1 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 T9 T1 P9 P1 M9 M1 J8 J2 G8 E1 B3 A9 VSSQ9 VSSQ8 VSSQ7 VSSQ6 VSSQ5 VSSQ4 VSSQ3 VSSQ2 VSSQ1 G9 G1 F9 E8 E2 D8 D1 B9 B1 C BGA96 BOM PROPERTY MB_CLK_TERM_RC R1U8 1 U9F5 DDR3_4GBIT_X16 6 6 6 6 6 B 6 A BI BI BI BI IN IN MB_DQSU_0_P MB_DQSU_0_N MB_DQSL_0_P MB_DQSL_0_N MB_RESET_N MB_A<15..0> C7 B7 F3 G3 T2 DQSU_P DQSU_N DQSL_P DQSL_N RESET_N 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M7 T7 T3 N7 R7 L7 R3 T8 R2 R8 P2 P8 N2 P3 P7 N3 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 0 M3 N8 M2 BA2 BA1 BA0 36.5 OHM 1% I11 CH 2 402 MEM CK_P CK_N J7 K7 R1U9 1 36.5 OHM 1% CH 2 402 MB_CLK0_DP MB_CLK0_DN 1 I82 C1U4 0.1 UF 10% 6.3 V X5R 402 2 IN IN MEM U8F3 DDR3_4GBIT_X16 6 6 6 6 6 6 6 6 6 IN MB_BA<2..0> 6 6 6 6 6 IN IN IN IN IN MB_WE_N MB_CAS_N MB_RAS_N MB_DMU_0 MB_DML_0 L3 K3 J3 D3 E7 WE_N CAS_N RAS_N DMU DML 18 18 IN IN MB_VREFCAA MB_VREFDQA M8 H1 VREFCA VREFDQ X866978-001 DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0 A3 B8 A2 A7 C2 C8 C3 D7 MB_DQ15 MB_DQ14 MB_DQ13 MB_DQ12 MB_DQ11 MB_DQ10 MB_DQ9 MB_DQ8 BI BI BI BI BI BI BI BI 6 6 6 6 6 6 6 6 DQL7 DQL6 DQL5 DQL4 DQL3 DQL2 DQL1 DQL0 H7 G2 H8 H3 F8 F2 F7 E3 MB_DQ7 MB_DQ6 MB_DQ5 MB_DQ4 MB_DQ3 MB_DQ2 MB_DQ1 MB_DQ0 BI BI BI BI BI BI BI BI 6 6 6 6 6 6 6 6 CKE CS_N K9 L2 MB_CKE0 MB_CS0_N IN IN 6 6 ODT ZQ K1 L8 MB_ODT0 MB_ZQ0 IN 6 1 BGA96 R9F19 BI BI BI BI IN IN MB_DQSU_1_P MB_DQSU_1_N MB_DQSL_1_P MB_DQSL_1_N MB_RESET_N MB_A<15..0> C7 B7 F3 G3 T2 DQSU_P DQSU_N DQSL_P DQSL_N RESET_N 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M7 T7 T3 N7 R7 L7 R3 T8 R2 R8 P2 P8 N2 P3 P7 N3 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 0 M3 N8 M2 BA2 BA1 BA0 6 IN MB_BA<2..0> 6 6 6 6 6 IN IN IN IN IN MB_WE_N MB_CAS_N MB_RAS_N MB_DMU_1 MB_DML_1 L3 K3 J3 D3 E7 WE_N CAS_N RAS_N DMU DML 18 18 IN IN MB_VREFCAB MB_VREFDQB M8 H1 VREFCA VREFDQ 243 OHM 1% 2 CH 402 CK_P CK_N J7 K7 DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0 A3 B8 A2 A7 C2 C8 C3 D7 DQL7 DQL6 DQL5 DQL4 DQL3 DQL2 DQL1 DQL0 H7 G2 H8 H3 F8 F2 F7 E3 CKE CS_N ODT ZQ MB_CLK0_DP MB_CLK0_DN IN IN MB_DQ31 MB_DQ30 MB_DQ29 MB_DQ28 MB_DQ27 MB_DQ26 MB_DQ25 MB_DQ24 B BI BI BI BI BI BI BI BI 6 6 6 6 6 6 6 6 MB_DQ23 MB_DQ22 MB_DQ21 MB_DQ20 MB_DQ19 MB_DQ18 MB_DQ17 MB_DQ16 BI BI BI BI BI BI BI BI 6 6 6 6 6 6 6 6 K9 L2 MB_CKE0 MB_CS0_N IN IN 6 6 K1 L8 MB_ODT0 MB_ZQ1 IN R8F12 6 1 X866978-001 6 6 A 243 OHM 1% 2 CH 402 BGA96 [PAGE_TITLE=MEMORY PARTITION C, LOW] MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 18/72 2 CSA PAGE 18/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 MEMORY CHANNEL B V_MEMIOAB BYTE LANE 4 BYTE LANE 5 I37 D C MEM U8F2 DDR3_4GBIT_X16 R9 R1 N9 N1 K8 K2 G7 D9 B2 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 H9 H2 F1 E9 D2 C9 C1 A8 A1 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 X866978-001 V_MEMIOAB BYTE LANE 6 BYTE LANE 7 V_MEMIOAB R8F17 1 KOHM 1% 2 CH 402 MB_VREFCAC 1 NC4 NC3 NC2 NC1 L9 L1 J9 J1 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 T9 T1 P9 P1 M9 M1 J8 J2 G8 E1 B3 A9 VSSQ9 VSSQ8 VSSQ7 VSSQ6 VSSQ5 VSSQ4 VSSQ3 VSSQ2 VSSQ1 G9 G1 F9 E8 E2 D8 D1 B9 B1 R8F18 1 KOHM 1% 2 CH 402 1 1 2 OUT 19 R8F15 1 KOHM 1% 2 CH 402 1 C8F3 1 UF 10% 6.3 V X5R 402 1 2 OUT 19 C8F2 1 UF 10% 6.3 V X5R 402 V_MEMIOAB R7F7 1 KOHM 1% 2 CH 402MB_VREFDQD OUT 1 R7F8 1 C3U11 1 KOHM 1 UF 1% 10% 6.3 V 2 CH 2 X5R 402 402 1 R8F1 1 KOHM 1% 2 CH 402 MB_VREFDQC OUT 1 R8F2 1 KOHM 1 C2U11 1% 1 UF 10% 2 CH 6.3 V 402 2 X5R BGA96 19 D MEM U8F1 DDR3_4GBIT_X16 V_MEMIOAB 1 I109 V_MEMIOAB R8F14 1 KOHM 1% 2 CH 402 MB_VREFCAD 1 19 R9 R1 N9 N1 K8 K2 G7 D9 B2 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 H9 H2 F1 E9 D2 C9 C1 A8 A1 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 X866978-001 NC4 NC3 NC2 NC1 L9 L1 J9 J1 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 T9 T1 P9 P1 M9 M1 J8 J2 G8 E1 B3 A9 VSSQ9 VSSQ8 VSSQ7 VSSQ6 VSSQ5 VSSQ4 VSSQ3 VSSQ2 VSSQ1 G9 G1 F9 E8 E2 D8 D1 B9 B1 C BGA96 402 MS_PART# U8F2,U8F1 I11 MATL EMPTY REF_DES EMPTY TRUEDESCR. DUMMY_BOM MEMORY BOM PROPERTY I166 MEM U8F2 DDR3_4GBIT_X16 6 6 6 6 6 6 B MB_DQSU_2_P MB_DQSU_2_N MB_DQSL_2_P MB_DQSL_2_N MB_RESET_N MB_A<15..0> C7 B7 F3 G3 T2 DQSU_P DQSU_N DQSL_P DQSL_N RESET_N 12 11 10 9 8 7 6 5 4 3 2 1 0 M7 T7 T3 N7 R7 L7 R3 T8 R2 R8 P2 P8 N2 P3 P7 N3 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 0 M3 N8 M2 BA2 BA1 BA0 L3 K3 J3 D3 E7 WE_N CAS_N RAS_N DMU DML M8 H1 VREFCA VREFDQ 15 14 13 IN MB_BA<2..0> 6 6 6 6 6 IN IN IN IN IN MB_WE_N MB_CAS_N MB_RAS_N MB_DMU_2 MB_DML_2 19 19 IN IN MB_VREFCAC MB_VREFDQC 6 A BI BI BI BI IN IN X866978-001 CK_P CK_N MEM U8F1 DDR3_4GBIT_X16 J7 K7 MB_CLK0_DP MB_CLK0_DN IN IN DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0 A3 B8 A2 A7 C2 C8 C3 D7 MB_DQ47 MB_DQ46 MB_DQ45 MB_DQ44 MB_DQ43 MB_DQ42 MB_DQ41 MB_DQ40 BI BI BI BI BI BI BI BI 6 6 6 6 6 6 6 6 DQL7 DQL6 DQL5 DQL4 DQL3 DQL2 DQL1 DQL0 H7 G2 H8 H3 F8 F2 F7 E3 MB_DQ39 MB_DQ38 MB_DQ37 MB_DQ36 MB_DQ35 MB_DQ34 MB_DQ33 MB_DQ32 BI BI BI BI BI BI BI BI 6 6 6 6 6 6 6 6 CKE CS_N K9 L2 MB_CKE0 MB_CS0_N IN IN 6 6 ODT ZQ K1 L8 MB_ODT0 MB_ZQ2 IN 6 1 BGA96 6 6 6 6 6 6 6 6 MB_DQSU_3_P MB_DQSU_3_N MB_DQSL_3_P MB_DQSL_3_N MB_RESET_N MB_A<15..0> C7 B7 F3 G3 T2 DQSU_P DQSU_N DQSL_P DQSL_N RESET_N 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M7 T7 T3 N7 R7 L7 R3 T8 R2 R8 P2 P8 N2 P3 P7 N3 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 0 M3 N8 M2 BA2 BA1 BA0 IN MB_BA<2..0> 6 6 6 6 6 IN IN IN IN IN MB_WE_N MB_CAS_N MB_RAS_N MB_DMU_3 MB_DML_3 L3 K3 J3 D3 E7 WE_N CAS_N RAS_N DMU DML 19 19 IN IN MB_VREFCAD MB_VREFDQD M8 H1 VREFCA VREFDQ 6 R8F11 BI BI BI BI IN IN 243 OHM 1% 2 CH 402 X866978-001 CK_P CK_N J7 K7 MB_CLK0_DP MB_CLK0_DN IN IN DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0 A3 B8 A2 A7 C2 C8 C3 D7 MB_DQ63 MB_DQ62 MB_DQ61 MB_DQ60 MB_DQ59 MB_DQ58 MB_DQ57 MB_DQ56 BI BI BI BI BI BI BI BI 6 6 6 6 6 6 6 6 DQL7 DQL6 DQL5 DQL4 DQL3 DQL2 DQL1 DQL0 H7 G2 H8 H3 F8 F2 F7 E3 MB_DQ55 MB_DQ54 MB_DQ53 MB_DQ52 MB_DQ51 MB_DQ50 MB_DQ49 MB_DQ48 BI BI BI BI BI BI BI BI 6 6 6 6 6 6 6 6 CKE CS_N K9 L2 MB_CKE0 MB_CS0_N IN IN 6 6 ODT ZQ K1 L8 MB_ODT0 MB_ZQ3 IN 6 1 BGA96 6 6 B A R8F10 243 OHM 1% 2 CH 402 [PAGE_TITLE=MEMORY PARTITION C, HIGH] MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 19/72 2 CSA PAGE 19/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 MEMORY CHANNEL B, DECOUPLING + TERMINATION D D PARTITION B DECOUPLING V_MEMIOAB V_VTTB V_VTTB 1 6 MB_A<15..0> IN 6 IN MB_WE_N 6 IN MB_CAS_N 6 IN MB_RAS_N R1U14 15 1 2 36.5 OHM 1% CH 402 R1U18 14 C 13 12 11 10 9 8 B 7 6 5 1 2 36.5 OHM1% CH 402 1 2 36.5 OHM1% CH 402 1 2 36.5 OHM 1% CH 402 IN 6 IN MB_CS0_N C9F9 22 UF 20% 6.3 V X7R 805 2 1 2 C7F5 22 UF 20% 6.3 V X7R 805 1 2 C8F5 22 UF 20% 6.3 V X7R 805 R1U11 1 2 36.5 OHM1% CH 402 R1U10 1 2 36.5 OHM1% CH 402 V_MEMIOAB MEMORY B, CHIP 0 DECOUPLING R8F22 1 2 36.5 OHM1% CH 402 1 R1U12 1 2 36.5 OHM1% CH 402 2 I140 C2U16 1 C3U5 1 2 2 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 I137 C3U2 1 UF 10% 6.3 V X5R 402 1 2 I138 I139 C3U13 1 C3U17 1 C2U8 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 1 C2U5 1 UF 10% 6.3 V X5R 402 2 C2U23 C 1 UF 10% 6.3 V X5R 402 1 2 36.5 OHM1% CH 402 V_MEMIOAB MEMORY B, CHIP 1, DECOUPLING R9F28 1 2 36.5 OHM 1% CH 402 1 V_VTTB R9F25 1 2 36.5 OHM 1% CH 402 2 R1U19 6 1 2 36.5 OHM 1% CH 402 MB_BA<2..0> IN 2 R9F24 1 1 2 36.5 OHM1% CH 402 R1U20 0 1 2 36.5 OHM 1% CH 402 I136 C2U2 1 UF 10% 6.3 V X5R 402 1 2 C2U3 1 UF 10% 6.3 V X5R 402 1 2 I141 I142 C2U14 1 C2U9 1 2 2 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 C2U6 1 UF 10% 6.3 V X5R 402 1 2 I143 C2U17 1 C2U19 1 C2U21 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 2 R1U15 1 2 36.5 OHM1% CH 402 B R9F23 1 2 36.5 OHM 1% CH 402 V_MEMIOAB R8F24 MEMORY B, CHIP 2, DECOUPLING 1 2 36.5 OHM1% CH 402 1 R1U17 1 2 36.5 OHM 1% CH 402 2 R1U16 I144 C2U1 1 UF 10% 6.3 V X5R 402 1 2 C2U4 1 UF 10% 6.3 V X5R 402 1 2 I145 C2U15 1 C2U10 1 C2U7 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 1 2 I146 I147 C2U18 1 C2U20 1 C2U22 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 R8F25 V_MEMIOAB R9F26 1 2 36.5 OHM 1% CH 402 MEMORY B, CHIP 3, DECOUPLING R9F30 1 2 36.5 OHM 1% CH 402 1 R9F27 1 2 36.5 OHM 1% CH 402 2 I148 C1U5 1 UF 10% 6.3 V X5R 402 1 2 I149 C1U8 1 UF 10% 6.3 V X5R 402 1 2 C1U9 1 UF 10% 6.3 V X5R 402 1 2 C1U6 1 UF 10% 6.3 V X5R 402 1 2 I150 C1U7 1 UF 10% 6.3 V X5R 402 1 2 C1U10 1 C1U11 1 C1U12 1 UF 10% 6.3 V X5R 402 [PAGE_TITLE=MEMORY PARTITION C, DECOUPLING, TERMINATION] MICROSOFT CONFIDENTIAL 8 1 R8F23 1 2 36.5 OHM1% CH 402 1 2 36.5 OHM 1% CH 402 0 6 2 1 2 36.5 OHM1% CH 402 22 UF 20% 6.3 V X7R 805 R9F31 3 A MB_ODT0 MB_CKE0 R9F29 1 2 36.5 OHM 1% CH 402 1 IN R1U21 4 2 6 R1U13 1 C8F6 7 6 5 4 3 2 1 UF 10% 6.3 V X5R 402 2 A 1 UF 10% 6.3 V X5R 402 PROJECT NAME PAGE GREYBULL_RETAIL 20/72 2 CSA PAGE 20/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 MEMORY CHANNEL A V_MEMIOAB BYTE LANE 0 BYTE LANE 1 I58 D C MEM U7F2 DDR3_4GBIT_X16 R9 R1 N9 N1 K8 K2 G7 D9 B2 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 H9 H2 F1 E9 D2 C9 C1 A8 A1 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 X866978-001 BYTE LANE 2 BYTE LANE 3 V_MEMIOAB R7F16 1 KOHM 1% 2 CH 402 MA_VREFCAA L9 L1 J9 J1 R7F13 1 KOHM 1% 2 CH 402 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 T9 T1 P9 P1 M9 M1 J8 J2 G8 E1 B3 A9 VSSQ9 VSSQ8 VSSQ7 VSSQ6 VSSQ5 VSSQ4 VSSQ3 VSSQ2 VSSQ1 G9 G1 F9 E8 E2 D8 D1 B9 B1 21 OUT MA_VREFCAB R7F17 1 KOHM 1% 2 CH 402 1 1 2 C7F2 R7F14 1 KOHM 1% 2 CH 402 1 1 UF 10% 6.3 V X5R 402 1 2 OUT 21 C7F1 1 UF 10% 6.3 V X5R 402 V_MEMIOAB V_MEMIOAB R7F5 1 KOHM 1% 2 CH 402 MA_VREFDQA OUT 1 R7F6 1 KOHM 1 C3U10 1% 1 UF 10% 2 CH 6.3 V 402 2 X5R 1 R6F7 1 KOHM 1% 2 CH 402 MA_VREFDQB OUT 1 R6F8 1 C4U10 1 KOHM 1 UF 1% 10% 6.3 V 2 CH 2 X5R 402 402 1 21 402 BGA96 21 U7F2 DDR3_4GBIT_X16 6 6 6 6 6 6 B A BI BI BI BI IN IN MA_DQSU_0_P MA_DQSU_0_N MA_DQSL_0_P MA_DQSL_0_N MA_RESET_N MA_A<15..0> 6 IN MA_BA<2..0> 6 6 6 6 6 IN IN IN IN IN MA_WE_N MA_CAS_N MA_RAS_N MA_DMU_0 MA_DML_0 21 21 IN IN MA_VREFCAA MA_VREFDQA C7 B7 F3 G3 T2 DQSU_P DQSU_N DQSL_P DQSL_N RESET_N 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M7 T7 T3 N7 R7 L7 R3 T8 R2 R8 P2 P8 N2 P3 P7 N3 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 0 M3 N8 M2 BA2 BA1 BA0 L3 K3 J3 D3 E7 WE_N CAS_N RAS_N DMU DML M8 H1 VREFCA VREFDQ 1 CK_P CK_N J7 K7 MA_CLK0_DP MA_CLK0_DN IN IN 6 6 6 6 6 6 A3 B8 A2 A7 C2 C8 C3 D7 MA_DQ15 MA_DQ14 MA_DQ13 MA_DQ12 MA_DQ11 MA_DQ10 MA_DQ9 MA_DQ8 BI BI BI BI BI BI BI BI 6 6 6 6 6 6 6 6 DQL7 DQL6 DQL5 DQL4 DQL3 DQL2 DQL1 DQL0 H7 G2 H8 H3 F8 F2 F7 E3 MA_DQ7 MA_DQ6 MA_DQ5 MA_DQ4 MA_DQ3 MA_DQ2 MA_DQ1 MA_DQ0 BI BI BI BI BI BI BI BI 6 6 6 6 6 6 6 6 CKE CS_N K9 L2 MA_CKE0 MA_CS0_N IN IN 6 6 ODT ZQ K1 L8 MA_ODT0 MA_ZQ0 IN 6 BGA96 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 H9 H2 F1 E9 D2 C9 C1 A8 A1 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 R7F11 243 OHM 1% 2 CH 402 BI BI BI BI IN IN MA_DQSU_1_P MA_DQSU_1_N MA_DQSL_1_P MA_DQSL_1_N MA_RESET_N MA_A<15..0> C7 B7 F3 G3 T2 DQSU_P DQSU_N DQSL_P DQSL_N RESET_N 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M7 T7 T3 N7 R7 L7 R3 T8 R2 R8 P2 P8 N2 P3 P7 N3 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 0 M3 N8 M2 BA2 BA1 BA0 6 IN MA_BA<2..0> 6 6 6 6 6 IN IN IN IN IN MA_WE_N MA_CAS_N MA_RAS_N MA_DMU_1 MA_DML_1 L3 K3 J3 D3 E7 WE_N CAS_N RAS_N DMU DML 21 21 IN IN MA_VREFCAB MA_VREFDQB M8 H1 VREFCA VREFDQ L9 L1 J9 J1 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 T9 T1 P9 P1 M9 M1 J8 J2 G8 E1 B3 A9 VSSQ9 VSSQ8 VSSQ7 VSSQ6 VSSQ5 VSSQ4 VSSQ3 VSSQ2 VSSQ1 G9 G1 F9 E8 E2 D8 D1 B9 B1 C BGA96 MATL EMPTY REF_DES EMPTY MEMORY TRUEDESCR. DUMMY_BOM CK_P CK_N J7 K7 MA_CLK0_DP MA_CLK0_DN IN IN DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0 A3 B8 A2 A7 C2 C8 C3 D7 MA_DQ31 MA_DQ30 MA_DQ29 MA_DQ28 MA_DQ27 MA_DQ26 MA_DQ25 MA_DQ24 BI BI BI BI BI BI BI BI 6 6 6 6 6 6 6 6 DQL7 DQL6 DQL5 DQL4 DQL3 DQL2 DQL1 DQL0 H7 G2 H8 H3 F8 F2 F7 E3 MA_DQ23 MA_DQ22 MA_DQ21 MA_DQ20 MA_DQ19 MA_DQ18 MA_DQ17 MA_DQ16 BI BI BI BI BI BI BI BI 6 6 6 6 6 6 6 6 CKE CS_N K9 L2 MA_CKE0 MA_CS0_N IN IN 6 6 ODT ZQ K1 L8 MA_ODT0 MA_ZQ1 IN R7F10 6 1 X866978-001 MS_PART# U7F2,U7F1 NC4 NC3 NC2 NC1 MEM U7F1 DDR3_4GBIT_X16 6 6 DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0 1 X866978-001 2 D I82 C4T6 0.1 UF 10% 6.3 V X5R 402 R4T10 1 36.5 OHM 1% CH 2 402 R9 R1 N9 N1 K8 K2 G7 D9 B2 X866978-001 MA_CLK_TERM_RC R4T12 1 36.5 OHM I36 1% CH 2 MEM 402 I111 MEM U7F1 DDR3_4GBIT_X16 1 1 NC4 NC3 NC2 NC1 V_MEMIOAB V_MEMIOAB 6 6 B A 243 OHM 1% 2 CH 402 BGA96 BOM PROPERTY [PAGE_TITLE=MEMORY PARTITION D, LOW] MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 21/72 2 CSA PAGE 21/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 MEMORY CHANNEL A BYTE LANE 4 BYTE LANE 5 V_MEMIOAB I37 D C MEM U6E5 DDR3_4GBIT_X16 R9 R1 N9 N1 K8 K2 G7 D9 B2 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 H9 H2 F1 E9 D2 C9 C1 A8 A1 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 X866978-001 BYTE LANE 6 BYTE LANE 7 V_MEMIOAB V_MEMIOAB R6E27 1 KOHM 1% 2 CH 402 MA_VREFCAD 1 NC4 NC3 NC2 NC1 L9 L1 J9 J1 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 T9 T1 P9 P1 M9 M1 J8 J2 G8 E1 B3 A9 VSSQ9 VSSQ8 VSSQ7 VSSQ6 VSSQ5 VSSQ4 VSSQ3 VSSQ2 VSSQ1 G9 G1 F9 E8 E2 D8 D1 B9 B1 R6F2 1 KOHM 1% 2 CH 402 1 OUT 22 R6E24 1 KOHM 1% 2 CH 402 1 1 C6F3 1 UF 10% 6.3 V X5R 402 2 V_MEMIOAB 2 MEM U6E3 DDR3_4GBIT_X16 OUT 22 C6E14 1 UF 10% 6.3 V X5R 402 V_MEMIOAB R6E25 1 KOHM 1% 2 CH 402 MA_VREFDQC 1 R6E26 1 KOHM 1 C4T11 1% 1 UF 10% 2 CH 6.3 V 402 2 X5R R6E9 1 KOHM 1% 2 CH 402 MA_VREFDQD 1 R6E8 1 C4T1 1 KOHM 1 UF 1% 10% 6.3 V 2 CH 2 X5R 402 402 1 1 BGA96 1 OUT 22 402 OUT 22 R9 R1 N9 N1 K8 K2 G7 D9 B2 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 H9 H2 F1 E9 D2 C9 C1 A8 A1 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 X866978-001 MS_PART# U6E5,U6E3 I11 MATL EMPTY REF_DES EMPTY TRUEDESCR. DUMMY_BOM MEMORY B 6 6 MA_DQSU_2_P MA_DQSU_2_N MA_DQSL_2_P MA_DQSL_2_N MA_RESET_N MA_A<15..0> C7 B7 F3 G3 T2 DQSU_P DQSU_N DQSL_P DQSL_N RESET_N 12 11 10 9 8 7 6 5 4 3 2 1 0 M7 T7 T3 N7 R7 L7 R3 T8 R2 R8 P2 P8 N2 P3 P7 N3 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 0 M3 N8 M2 BA2 BA1 BA0 L3 K3 J3 D3 E7 WE_N CAS_N RAS_N DMU DML M8 H1 VREFCA VREFDQ 15 14 13 IN MA_BA<2..0> 6 6 6 6 6 IN IN IN IN IN MA_WE_N MA_CAS_N MA_RAS_N MA_DMU_2 MA_DML_2 22 22 IN IN MA_VREFCAC MA_VREFDQC 6 A BI BI BI BI IN IN X866978-001 CK_P CK_N L9 L1 J9 J1 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 T9 T1 P9 P1 M9 M1 J8 J2 G8 E1 B3 A9 VSSQ9 VSSQ8 VSSQ7 VSSQ6 VSSQ5 VSSQ4 VSSQ3 VSSQ2 VSSQ1 G9 G1 F9 E8 E2 D8 D1 B9 B1 C BGA96 I78 MEM U6E3 DDR3_4GBIT_X16 J7 K7 MA_CLK0_DP MA_CLK0_DN IN IN 6 6 A3 B8 A2 A7 C2 C8 C3 D7 MA_DQ47 MA_DQ46 MA_DQ45 MA_DQ44 MA_DQ43 MA_DQ42 MA_DQ41 MA_DQ40 BI BI BI BI BI BI BI BI 6 6 6 6 6 6 6 6 DQL7 DQL6 DQL5 DQL4 DQL3 DQL2 DQL1 DQL0 H7 G2 H8 H3 F8 F2 F7 E3 MA_DQ39 MA_DQ38 MA_DQ37 MA_DQ36 MA_DQ35 MA_DQ34 MA_DQ33 MA_DQ32 BI BI BI BI BI BI BI BI 6 6 6 6 6 6 6 6 CKE CS_N K9 L2 MA_CKE0 MA_CS0_N IN IN 6 6 ODT ZQ K1 L8 MA_ODT0 MA_ZQ2 IN 6 1 6 6 6 6 6 6 DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0 BGA96 NC4 NC3 NC2 NC1 BOM PROPERTY MEM U6E5 DDR3_4GBIT_X16 6 6 6 6 D I109 V_MEMIOAB R6F1 1 KOHM 1% 2 CH 402 MA_VREFCAC 1 MA_DQSU_3_P MA_DQSU_3_N MA_DQSL_3_P MA_DQSL_3_N MA_RESET_N MA_A<15..0> C7 B7 F3 G3 T2 DQSU_P DQSU_N DQSL_P DQSL_N RESET_N 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M7 T7 T3 N7 R7 L7 R3 T8 R2 R8 P2 P8 N2 P3 P7 N3 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 1 0 M3 N8 M2 BA2 BA1 BA0 IN MA_BA<2..0> 6 6 6 6 6 IN IN IN IN IN MA_WE_N MA_CAS_N MA_RAS_N MA_DMU_3 MA_DML_3 L3 K3 J3 D3 E7 WE_N CAS_N RAS_N DMU DML 22 22 IN IN MA_VREFCAD MA_VREFDQD M8 H1 VREFCA VREFDQ 6 R6F3 BI BI BI BI IN IN 243 OHM 1% 2 CH 402 X866978-001 CK_P CK_N J7 K7 MA_CLK0_DP MA_CLK0_DN IN IN DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0 A3 B8 A2 A7 C2 C8 C3 D7 MA_DQ63 MA_DQ62 MA_DQ61 MA_DQ60 MA_DQ59 MA_DQ58 MA_DQ57 MA_DQ56 BI BI BI BI BI BI BI BI 6 6 6 6 6 6 6 6 DQL7 DQL6 DQL5 DQL4 DQL3 DQL2 DQL1 DQL0 H7 G2 H8 H3 F8 F2 F7 E3 MA_DQ55 MA_DQ54 MA_DQ53 MA_DQ52 MA_DQ51 MA_DQ50 MA_DQ49 MA_DQ48 BI BI BI BI BI BI BI BI 6 6 6 6 6 6 6 6 CKE CS_N K9 L2 MA_CKE0 MA_CS0_N IN IN 6 6 ODT ZQ K1 L8 MA_ODT0 MA_ZQ3 IN 6 1 BGA96 6 6 B A R6E22 243 OHM 1% 2 CH 402 [PAGE_TITLE=MEMORY PARTITION D, HIGH] MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 22/72 2 CSA PAGE 22/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 MEMORY CHANNEL A, DECOUPLING + TERMINATION D D PARTITION A DECOUPLING V_MEMIOAB V_VTTA V_VTTA 1 6 IN MA_A<15..0> IN MA_WE_N 1 2 36.5 OHM 1% CH 402 6 IN MA_CAS_N 1 2 36.5 OHM1% CH 402 6 IN MA_RAS_N 1 2 36.5 OHM 1% CH 402 6 IN MA_ODT0 R6E12 15 C 1 2 36.5 OHM1% CH 402 R4T11 14 13 12 11 10 9 B 1 2 36.5 OHM1% CH 402 R4T9 1 2 36.5 OHM1% CH 402 MA_CS0_N 2 2 C7F3 22 UF 20% 6.3 V X7R 805 MEMORY A, CHIP 0 DECOUPLING C R6E6 I136 1 C3U7 1 UF 10% 6.3 V X5R 402 R4T8 1 2 36.5 OHM 1% CH 402 1 2 36.5 OHM 1% CH 402 2 1 2 I137 C3U9 1 UF 10% 6.3 V X5R 402 I138 1 1 C3U15 1 UF 10% 6.3 V X5R 402 2 1 C3U4 1 UF 10% 6.3 V X5R 402 2 1 C3U1 1 UF 10% 6.3 V X5R 402 2 1 C3U12 1 UF 10% 6.3 V X5R 402 2 1 C3U16 1 UF 10% 6.3 V X5R 402 2 2 C3U19 1 UF 10% 6.3 V X5R 402 R4T4 V_MEMIOAB MEMORY A, CHIP 1, DECOUPLING 1 V_VTTA R4T2 1 2 36.5 OHM1% CH 402 R6E18 2 6 R6E2 IN MA_BA<2..0> 2 1 R6E20 0 1 2 36.5 OHM1% CH 402 C4U9 1 UF 10% 6.3 V X5R 402 1 2 36.5 OHM1% CH 402 4 1 2 36.5 OHM1% CH 402 3 1 2 36.5 OHM1% CH 402 2 1 2 36.5 OHM1% CH 402 2 I139 1 C3U3 1 UF 10% 6.3 V X5R 402 2 I140 C4U11 1 UF 10% 6.3 V X5R 402 1 2 1 C3U8 1 UF 10% 6.3 V X5R 402 2 1 C3U6 1 UF 10% 6.3 V X5R 402 2 I141 1 C3U14 1 UF 10% 6.3 V X5R 402 1 C3U18 1 UF 10% 6.3 V X5R 402 2 2 C4U12 1 UF 10% 6.3 V X5R 402 B R4T5 1 2 36.5 OHM1% CH 402 R6E21 1 2 36.5 OHM 1% CH 402 V_MEMIOAB MEMORY A, CHIP 2, DECOUPLING R6E4 1 2 36.5 OHM1% CH 402 1 R4T3 5 1 2 C4U3 1 UF 10% 6.3 V X5R 402 1 2 I142 I143 I144 C4T12 1 C4T18 1 C4T17 1 C4T16 1 C4T15 1 C4T14 1 C4T13 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 2 2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 R6E17 R6E3 V_MEMIOAB MEMORY A, CHIP 3, DECOUPLING R6E1 1 R6E15 1 2 36.5 OHM1% CH 402 2 R6E10 I145 1 C4T10 1 UF 10% 6.3 V X5R 402 2 C4T2 1 UF 10% 6.3 V X5R 402 1 2 A C4T9 1 UF 10% 6.3 V X5R 402 1 2 I146 C4T8 1 UF 10% 6.3 V X5R 402 1 2 C4T7 1 UF 10% 6.3 V X5R 402 1 2 I147 C4T5 1 UF 10% 6.3 V X5R 402 1 2 I148 C4T4 1 UF 10% 6.3 V X5R 402 1 2 C4T3 1 UF 10% 6.3 V X5R 402 1 2 36.5 OHM1% CH 402 [PAGE_TITLE=MEMORY PARTITION D, DECOUPLING, TERMINATION] 8 2 1 C7F4 22 UF 20% 6.3 V X7R 805 V_MEMIOAB 1 2 36.5 OHM1% CH 402 1 2 36.5 OHM1% CH 402 1 2 36.5 OHM1% CH 402 0 IN R4T7 R6E13 7 1 6 1 C6E18 22 UF 20% 6.3 V X7R 805 R6E5 1 2 36.5 OHM1% CH 402 1 2 36.5 OHM1% CH 402 A IN 2 22 UF 20% 6.3 V X7R 805 R6E16 8 6 6 MA_CKE0 R6E14 1 2 36.5 OHM1% CH 402 R4T6 6 1 C6E3 7 6 5 4 MICROSOFT CONFIDENTIAL 3 PROJECT NAME PAGE GREYBULL_RETAIL 23/72 2 CSA PAGE 23/72 1 FAB REV M 1.0 8 7 6 5 4 U4D2 KIC, USB 6 of 11 3 2 1 IC KIC I84 USBD_D0_DP AF8 BI 36 USBD_D0_DN AE8 USB2_WIFI_DN BI 36 USBC_D0_DP AC4 USB2_AUX_DP BI 36 USBC_D0_DN AC3 USB2_AUX_DN BI 36 USB3_AUX_TP OUT 36 USB3_AUX_TN OUT 36 USB3_BP_P1_TP OUT 35 USB3_BP_P1_TN OUT 35 USB2_BP_P1_DP BI 35 USB2_BP_P1_DN BI 35 USB2_WIFI_DP D D 1 36 IN USB3_AUX_RP 36 IN USB3_AUX_RN Y1 USBC_D1_RXP Y2 USBC_D1_RXN USBC_D1_TXP W3 USB3_AUX_TP_C USBC_D1_TXN W4 USB3_AUX_TN_C C6B9 2 0.1 UF 10% 6.3 V X5R 402 1 C6B8 2 0.1 UF 10% X5R 402 6.3 V 1 35 35 IN USB3_BP_P1_RP V1 USBB_D2_RXP USBB_D2_TXP U3 USB3_BP_P1_TP_C IN USB3_BP_P1_RN V2 USBB_D2_RXN USBB_D2_TXN U4 USB3_BP_P1_TN_C C C7B10 0.1 UF 10% X5R 402 6.3 V 1 35 IN 35 IN USB3_BP_P0_RN T1 USBB_D3_RXP T2 USBB_D3_RXN AE4 USBB_D0_DN AE3 USBB_D1_DP AD2 USB2_BP_P0_DP BI 35 USBB_D1_DN AD1 USB2_BP_P0_DN BI 35 USB3_BP_P0_TP OUT 35 USB3_BP_P0_TN OUT 35 USB3_FP_P0_TP OUT 35 USB3_FP_P0_TN OUT 35 USB2_FP_P0_DP BI 35 USB2_FP_P0_DN BI 35 USBB_D3_TXP R3 USB3_BP_P0_TP_C USBB_D3_TXN R4 USB3_BP_P0_TN_C DB4B2 2 1 IN USB3_FP_P0_RP AA8 USBA_D2_RXP USBA_D2_TXP AB10 USB3_FP_P0_TP_C IN USB3_FP_P0_RN AA7 USBA_D2_RXN USBA_D2_TXN AB9 C3F4 USB3_FP_P0_TN_C AC8 USBA_D1_DP AF6 USB2_ACC_DP BI 36 USBA_D1_DN AF5 USB2_ACC_DN BI 36 USB3_TP_P1_TP_C USB3_TP_P1_TN_C USBA_D3_RXP USBA_D3_TXP AA3 1 USB3_TP_P1_RN AB2 USBA_D3_RXN USBA_D3_TXN AA4 C4B8 2 0.1 UF 10% 6.3 V USB3_TP_P1_TP 1 174 OHM 1% 2 CH 402 8 7 6 AB11 USBA_D1_TXRTUNE X861949-001 5 USBA_D2_AMOUT USBA_D1_AMOUT USBA_D0_AMOUT AA5 USBA_D2_AMOUNT AE6 USBA_D1_AMOUNT AC11 USBA_D0_AMOUNT 1 1 1 USBB_D2_AMOUT USBB_D1_AMOUT USBB_D0_AMOUT R5 AD5 AF4 USBB_D2_AMOUNT USBB_D1_AMOUNT USBB_D0_AMOUNT 1 1 1 USBC_D1_AMOUT USBC_D0_AMOUT W5 AC5 USBC_D1_AMOUNT USBC_D0_AMOUNT 1 1 USBD_D0_AMOUT AE9 USBD_D0_AMOUNT 1 C4B7 2 USB3_TP_P1_TN 1 DB4B4 A 0.1 UF 10% 402 6.3 V X5R DB6P4 DB4C2 DB4D4 DB6P7 DB4C3 DB4D1 DB6P5 DB6P6 DB3D8 MICROSOFT CONFIDENTIAL BGA515 4 DB4B5 X5R 402 1 R6R19 2 0.1 UF 10% 402 6.3 V X5R USBA_D0_DN AB1 USBA_D1_TXRTUNE C3F5 AC7 USB3_TP_P1_RP B X5R 402 USBA_D0_DP 1 1 2 2 1 A C7B11 0.1 UF 10% X5R 402 6.3 V 0.1 UF 10% 6.3 V 1 DB4B3 C7B12 C 0.1 UF 10% X5R 402 6.3 V 1 35 2 USBB_D0_DP B 35 C7B9 0.1 UF 10% X5R 402 6.3 V 1 USB3_BP_P0_RP 2 3 PROJECT NAME PAGE GREYBULL_RETAIL 24/72 2 CSA PAGE 24/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 KIC, PCIEX + SATA + VIDEO D 1 I5 U4D2 2 2 2 2 IN IN IN IN PEX_L0_SOC_SB_TP_C PEX_L0_SOC_SB_TN_C PEX_L1_SOC_SB_TP_C PEX_L1_SOC_SB_TN_C D26 E26 A23 B23 PEX_RX0_DP PEX_RX0_DN PEX_RX1_DP PEX_RX1_DN 2 0.1 UF 10% X5R 402 6.3 V IC KIC 3 of 11 C4D2 C24 D24 C22 D22 PEX_TX0_DP PEX_TX0_DN PEX_TX1_DP PEX_TX1_DN 1 PEX_L0_SB_SOC_TP PEX_L0_SB_SOC_TN PEX_L1_SB_SOC_TP PEX_L1_SB_SOC_TN C5D9 2 1 C4D1 2 0.1 UF 10% X5R 402 6.3 V 0.1 UF 10% X5R 402 6.3 V 1 C5D12 2 D PEX_L0_SB_SOC_TP_C OUT 2 PEX_L0_SB_SOC_TN_C OUT 2 PEX_L1_SB_SOC_TP_C OUT 2 PEX_L1_SB_SOC_TN_C OUT 2 0.1 UF 10% X5R 402 6.3 V 39 39 39 39 IN IN IN IN SATA1_HDD_RP SATA1_HDD_RN SATA0_ODD_RP SATA0_ODD_RN B6 A6 B4 A4 SATA1_RX_DP SATA1_RX_DN SATA0_RX_DP SATA0_RX_DN SATA1_HDD_TP SATA1_HDD_TN SATA0_ODD_TP SATA0_ODD_TN D5 C5 D3 C3 SATA1_TX_DP SATA1_TX_DN SATA0_TX_DP SATA0_TX_DN OUT OUT OUT OUT C1 SATA_AMOUT B25 PEX_AMOUT SATA_AMOUT PEX_AMOUT 1 1 C X861949-001 39 39 39 39 DB5C1 DB6R1 C BGA515 1 V_3P3 1 V_SB1P1 1 R5R15 300 OHM 1% 2 CH 402 38 37 SOT23-3 1 2 NC 3 HDMI_RX_CEC_3P3 D4C2 BAS40LT B 1 1 DB6P3 IN HDMI_RX_REXT N3 KIC 7 of 11 IN IN M1 M2 TMDS_RX_DP2 TMDS_RX_DN2 37 37 IN IN TMDS_RX_DP1 TMDS_RX_DN1 L2 L3 TMDS_RX_DP1 TMDS_RX_DN1 37 37 IN IN TMDS_RX_DP0 TMDS_RX_DN0 K1 K2 TMDS_RX_DP0 TMDS_RX_DN0 37 37 IN IN TMDS_RX_CLKP TMDS_RX_CLKN J3 J2 TMDS_RX_CLK_P TMDS_RX_CLK_N HMDI_RX_TESTP HDMI_RX_TESTN K4 J4 TMDS_RX_TESTP TMDS_RX_TESTN P2 HDMI_RX_CEC 1 1 DB6P1 DB6P2 1 2 HDMI_RX_CEC_R 330 OHM 1% CH 402 SP1_TM1 2 IN DP1_HPD 1 D12 B8 R3T20 100 KOHM 1% 2 CH 402 DP_L1_SB_SOC_TP_C OUT 2 DP_L1_SB_SOC_TN_C OUT 2 DP_L0_SB_SOC_TP_C OUT 2 DP_L0_SB_SOC_TN_C OUT 2 DP_AUX_SB_SOC_TP_C OUT 2 DP_AUX_SB_SOC_TN_C OUT 2 0.1 UF 10% X5R 402 6.3 V 1 DP_TX_LANE1_P DP_TX_LANE1_N B10 DP_L1_SB_SOC_TP C10 DP_L1_SB_SOC_TN DP_TX_LANE0_P DP_TX_LANE0_N A9 DP_L0_SB_SOC_TP B9 DP_L0_SB_SOC_TN DP_TX_AUX_P DP_TX_AUX_N A11 DP_AUX_SB_SOC_TP B11 DP_AUX_SB_SOC_TN C5D4 2 0.1 UF 10% X5R 402 6.3 V C5D3 1 2 0.1 UF 10% X5R 402 6.3 V C5D8 1 2 0.1 UF 10% X5R 402 C5D7 6.3 V 1 2 B 0.1 UF 10% X5R 402 6.3 V 1 R4C5 HDMI_RX_CEC IC TMDS_RX_REXT TMDS_RX_DP2 TMDS_RX_DN2 37 37 R4C3 27 KOHM 5% 2 CH 402 U4D2 2 0.1 UF 10% X5R 402 6.3 V C5D5 1 2 I24 R6P8 2 KOHM 1% 2 CH 402 V_3P3STBY C5D6 HDMI_RX_HPD 37 R5R2 100 KOHM 1% 2 CH 402 1 V_3P3 R5R1 100 KOHM 1% 2 CH 402 DP_TX_HPD F11 DDA_LFCSENSE DDA_LFC F10 DDA_LFC DP_ATB X861949-001 2 OUT DP_TM1 DDA_LFCSENSE 1 P1 HDMI_RX_HPD C12 DP_ATB 1 DB5R1 BGA515 C6R35 0.1 UF 10% 6.3 V X5R 402 PLACE AS CLOSE AS POSSIBLE TO U4D2 PINS F10-F11 A A MS_PART# U4D2 MATL EMPTY REF_DES EMPTY TRUEDESCR. DUMMY_BOM KIC BOM PROPERTY MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 25/72 2 CSA PAGE 25/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 KIC, SMC V_3P3STBY R4D28 4.7 KOHM 5% EMPTY 402 D FT6R21 FTP 1 U4D2 KIC 1 4 of 11 SMC_UART1_TXD 65 29 OUT FT5N1 FT5N2 V_5P0 IN V22 SMC_P4_GPIO6 40 IN BINDSW_N T23 SMC_P4_GPIO5 U23 SMC_P4_GPIO4 IN 55 OUT VREG_V5P0_DUAL_SEL0 U22 SMC_P4_GPIO3 61 OUT VREG_3P3STBY_IN_SEL U21 SMC_P4_GPIO2 32 OUT ENET_RST_N T21 SMC_P4_GPIO1 FTP IN ENET_WAKE_N R23 SMC_P4_GPIO0 FTP 1 32 1 SMC_P3_GPIO7 1 R6R22 58 57 51 50 69 56 53 52 56 53 52 69 10 KOHM 5% 2 CH 402 1 R6R23 54 10 KOHM 5% 2 CH 402 54 69 R21 SMC_P3_GPIO2 IN R22 OUT VREG_PWRGPA_EN R6R6 BI OUT 37 BI OUT R5T11 2 KOHM 1% 2 CH 402 1 1 SMBUS_DATA FTP FT6R7 2 1 R4D38 IN R5T9 2 KOHM 1% 2 CH 70 402 R4D31 1 2 243 OHM 1% CH 402 SMC_RXD IN SMC_P2_GPIO5 OUT 39 SMC_P2_GPIO4 F1 ODD_3P3V_STBY_EN OUT 39 SMC_P2_GPIO3 G3 ODD_PWR_EN OUT 39 SMC_P2_GPIO2 H5 ODD_OPEN OUT 39 SMC_P2_GPIO1 J5 ODD_STATUS IN 39 SMC_P2_GPIO0 J6 ODD_WAKE_N IN 39 SMC_P1_GPIO7 J21 SOC_THERMTRIP_R 1 AE21 AD21 1 2 SB_SOC_CLK_R 243 OHM 1% CH 402 R5D2 1 2 49.9 OHM1% CH 402 1 SMBUS_DATA_R SMBUS_CLK_R AE20 AF20 HDMI_TX_DDC_DATA_SB HDMI_TX_DDC_CLK_SB H6 G6 HDMI_RX_DDC_DATA_SB HDMI_RX_DDC_CLK_SB G5 F5 R5T10 4.7 KOHM 5% 2 CH 402 SMC_P1_GPIO4 SMC_P1_GPIO3 J23 FAN_PWM SMC_P1_GPIO2 H25 SMC_P1_GPIO2 SMC_P1_GPIO1 J25 SMC_P1_GPIO1 SMC_UART1_CTS SMC_P1_GPIO0 H26 LED_NEXUS_R OUT 40 SMBUS3_SDA SMBUS3_SCK SMC_P0_GPIO7 M23 HDMI_V_5P0_EN OUT 38 SMC_P0_GPIO6 M24 PSU_V12P0_EN OUT 41 42 SMC_P0_GPIO5 L23 DP0_HPD SMC_P0_GPIO4 K24 SMC_P0_GPIO3 L25 40 OUT 1 1 FTP FT5R1 FTP FT5R2 SOC_THERMTRIP R5R5 1 2 0 OHM 5% CH 402 R5R12 1 2 0 OHM 5% CH 402 IN 8 SOC_PWR_OK OUT 8 44 68 SOC_RST_N OUT 68 8 SP_SMC_INT_N IN 8 B R5R6 1 4.7 KOHM 5% CH 2 402 1 1 FTP FT5R3 FTP FT4T1 SMBUS1_SDA SMBUS1_SCK SMBUS0_SDA SMBUS0_SCK IN 38 WIFI_RESET_N OUT 36 ENET_V_3P3STBY_EN OUT 32 1 2 0 OHM 5% CH 402 R5R34 R6R24 SMC_P0_GPIO2 M25 HDMI_RX_DDC_5V_E_R SMC_P0_GPIO1 L26 SMC_DBG_LED0_SWO OUT 65 SMC_P0_GPIO0 K26 VREG_SB1P8_EN OUT 60 SECURITY_BYPASS SMC_IR_IN R5R33 1 2 0 OHM 5% CH 402 1 2 0 OHM 5% CH 402 USB_AUX_EN OUT 36 IR_BLAST_EN OUT 63 IN 37 HDMI_RX_DDC_5V_E V_5P0STBY 1 2 49.9 OHM1% CH 402 X861949-001 A BGA515 2 V_5P0STBY 6 R5C27 HDMI_RX_DDC_CLK 1 2 0 OHM 5% CH 402 SP_SMC_INT_N_R D5C1 R5C28 HDMI_RX_DDC_DATA R5R9 SOC_RESET_N_R SMBUS2_SDA SMBUS2_SCK AC14 N26 1 2 49.9 OHM1% CH 402 1 R5R7 1 2 0 OHM 5% CH 402 K22 FTP FT6R20 R5D1 HDMI_TX_DDC_CLK SOC_PWR_OK_R R5R8 1 4.7 KOHM 5% CH 2 402 FTP FT6R19 R4D33 1 2 0 OHM 5% CH 402 H21 C V_SOC1P8 J22 SMC_UART1_RXD V26 SB_SOC_DATA_R 1 2 0 OHM 5% CH 402 HDMI_TX_DDC_DATA SMC_CTS 1 2 10 OHM 1% CH 402 D5C1 1 5 3 IR_DATA 4 7 MICROSOFT CONFIDENTIAL DIO THESE SIGNALS ARE NOT COMPLETE- ENDING IS CLK OR P AND N 8 68 SMC_P1_GPIO5 1 FT6R12 FTP IN V25 DIO 40 IN HDD_PWR_EN 1 FT6R11 FTP R4D39 SMBUS_CLK A 37 COLD_RESET_N G1 SMC_P3_GPIO0 R6R7 10 KOHM 5% CH 402 70 1 SB_SOC_CLK OUT OUT V_SOC1P8 R4D26 SB_SOC_DATA BI BI 1 402 F2 SMC_P2_GPIO6 SMC_P1_GPIO6 10 KOHM 5% CH 402 10 KOHM 5% 2 CH 44 45 SMC_P3_GPIO1 P23 I181 1 R9C64 IN G2 SMC_P3_GPIO4 VREG_PWRGPA_PWRGD 1.27 KOHM 1 R4D27 1% 1.27 KOHM 1% 2 CH 402 2 CH 402 38 N21 70 OUT V_5P0 VREG_CPUGFX_PWRGD SMC_P2_GPIO7 SMC_P3_GPIO5 VREG_PWRGPB_EN 1 38 OUT VREG_V5P0_EN N22 OUT FT6R6 FTP 10 KOHM 5% 2 CH 402 SMC_P3_GPIO6 SMC_P3_GPIO3 2 52 50 40 65 44 66 64 54 53 IN VREG_V5P0_PWRGD M22 P21 B 53 52 50 44 40 66 65 64 54 USB_AUX_OCP_FLT_N VREG_PWRGPB_PWRGD 1 8 IN R4F19 SMC_P3_GPIO7 IN V_3P3STBY 8 L21 FTP FT6R13 V24 SMC_RTS V_3P3STBY I21 V_5P0 70 OUT 1 SMC_UART1_RTS FTP FT6R14 SMC_TXD 1 INT_N 36 57 51 50 SMC_P4_GPIO7 T24 SMC_RST_N_IN EJECTSW_N 1 2 0 OHM 5% CH 402 C V23 AF23 IN R5E10 IR_BLAST_SMC_OUT SMC_RST_N 67 40 40 63 IN PWRSW_N 67 40 D IC 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 26/72 2 CSA PAGE 26/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 KIC, FACET D D FT6R15 FTP FT6R18 FTP 1 1 1 1 U4D2 65 C FT6T1 FTP FTCT3 FTP FT6T2 FTP 1 65 1 65 1 65 65 65 65 KIC 2 of 11 IN KER_DBG_CTS R26 IN KER_DBG_RXD U26 UART0_RXD IN SPI_SS_N AF13 SPI_SS_N IN SPI_MOSI AF11 SPI_MOSI IN SPI_CLK AE11 SPI_CLK_IN IN IN IN IN FT6R1 FT6R3 FT6R5 FT6R4 SB_TDI SB_TMS SB_TRST SB_TCK FTP FTP FTP FTP 1 1 1 1 AA13 AB14 AB12 AB13 UART0_CTS I38 IC UART0_TXD U25 KER_DBG_TXD OUT 65 UART0_RTS T25 KER_DBG_RTS OUT 65 SPI_MISO GPIO3 GPIO2 GPIO1 GPIO0 TDI TMS TRST TCK FTP FT6R16 FTP FT6R17 TDO POR_ATB 1 R4D3 AE12 SPI_MISO_R N24 P24 P25 P26 1 2 SPI_MISO 36.5 OHM1% CH 402 SMM_GPIO3 SMM_GPIO2 SMM_GPIO1 SMM_GPIO0 AA12 H22 SB_TDO POR_ATB OUT C FTP FT6T4 65 SMM_GPIO3 (N24) OVERLOADED ON SLT SYSTEMS BI BI BI BI OUT 1 65 DB6R2 TP X861949-001 BGA515 1 FTP FT6R2 R6R16 40 IN B FAN_TACH_IN 1 2 100 OHM 5% CH 402 B R5R21 38 OUT 1 2 HDMI_DP_OUT_SEL 100 OHM 5% CH 402 A A MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 27/72 2 CSA PAGE 27/72 1 FAB REV M 1.0 8 7 6 5 4 U4D2 AF1 AF2 AF3 AF7 AF9 AF10 AF12 AF15 AF17 AF19 AF21 AF24 AF25 AF26 AE1 AE2 AE5 AE7 AE16 AE22 AE23 AE24 AE25 AE26 AD3 AD4 AD6 AD8 AD9 AD18 AC12 AC13 AC15 AC17 AC19 AC20 AC21 AB16 AA14 AA18 V21 U24 T11 T12 T13 T15 T16 T22 T26 R11 R24 R25 P12 P14 P22 N15 N23 N25 M11 M14 M16 M21 M26 L5 L11 L12 L15 L16 I3 U4D2 D E9 A8 D10 D8 A10 C8 C9 C11 E11 C B DP_VSS[0] DP_VSS[1] DP_VSS[2] DP_VSS[3] DP_VSS[4] DP_VSS[5] DP_VSS[6] DP_VSS[7] DP_VSS[8] F4 E3 E5 D1 D2 D4 C2 C6 C4 B3 B2 B5 B7 A2 A3 A5 A7 B1 D6 SATA_VSS[0] SATA_VSS[1] SATA_VSS[2] SATA_VSS[3] SATA_VSS[4] SATA_VSS[5] SATA_VSS[6] SATA_VSS[7] SATA_VSS[8] SATA_VSS[9] SATA_VSS[10] SATA_VSS[11] SATA_VSS[12] SATA_VSS[13] SATA_VSS[14] SATA_VSS[15] SATA_VSS[16] SATA_VSS[17] SATA_VSS[18] R6 N1 N2 N4 N6 M3 M4 L1 L4 K3 J1 H2 H3 H4 HDMI_VSS[0] HDMI_VSS[1] HDMI_VSS[2] HDMI_VSS[3] HDMI_VSS[4] HDMI_VSS[5] HDMI_VSS[6] HDMI_VSS[7] HDMI_VSS[8] HDMI_VSS[9] HDMI_VSS[10] HDMI_VSS[11] HDMI_VSS[12] HDMI_VSS[13] F14 E16 E13 KIC 8 of 11 IC PEX_VSS[0] PEX_VSS[1] PEX_VSS[2] PEX_VSS[3] PEX_VSS[4] PEX_VSS[5] PEX_VSS[6] PEX_VSS[7] PEX_VSS[8] PEX_VSS[9] PEX_VSS[10] PEX_VSS[11] PEX_VSS[12] PEX_VSS[13] PEX_VSS[14] PEX_VSS[15] USB3_VSS[0] USB3_VSS[1] USB3_VSS[2] USB3_VSS[3] USB3_VSS[4] USB3_VSS[5] USB3_VSS[6] USB3_VSS[7] USB3_VSS[8] USB3_VSS[9] USB3_VSS[10] USB3_VSS[11] USB3_VSS[12] USB3_VSS[13] USB3_VSS[14] USB3_VSS[15] USB3_VSS[16] USB3_VSS[17] USB3_VSS[18] USB3_VSS[19] USB3_VSS[20] USB3_VSS[21] USB3_VSS[22] USB3_VSS[23] USB3_VSS[24] USB3_VSS[25] USB3_VSS[26] USB3_VSS[27] USB3_VSS[28] USB3_VSS[29] USB3_VSS[30] USB3_VSS[31] A26 A25 A24 A22 B26 B24 B22 C26 C25 C23 D25 D23 E25 E24 E22 F25 AC1 AC2 AC9 AC10 AB3 AB4 AB5 AB6 AB7 AB8 AA1 AA2 AA9 AA10 AA11 Y3 Y4 Y5 W1 W2 V3 V4 V5 U1 U2 T3 T4 T5 R1 R2 P3 P4 PLL_VSS[0] PLL_VSS[1] PLL_VSS[2] BGA515 X861949-001 KIC 9 of 11 VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] 3 2 1 I4 IC VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] L22 L24 K6 K21 K23 K25 J24 J26 H1 AB21 G4 G25 F3 F7 F8 F18 F23 E1 E21 AB22 AB23 AB24 D18 D19 AB25 C16 C17 C21 B12 AB26 AA19 AA20 B18 B19 A12 A17 H23 AB19 AB20 AC18 AC22 AC23 AC26 AD23 AD25 AB18 AD20 AD19 AE19 AA21 AA22 AA23 AA24 AA25 AA26 Y21 Y22 Y23 Y24 Y25 Y26 D13 D14 D15 C13 B13 B14 B15 A20 D C B BGA515 X861949-001 A A MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 28/72 2 CSA PAGE 28/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 V_12P0 KIC, CLOCKS + STRAPPING + POR U4D2 CONNECT BYPASS PIN TO BACKUP CLOCK D IC KIC 1 of 11 V_1P8STBY V_3P3 V_EXT_DET 1 G22 R5R16 V_EXT_OK 100 KOHM 5% 2 CH 402 1 249 KOHM 1% 402 CH Y5D1 25 MHZ 1 C 2 C5D11 22 PF 5% 50 V NPO 402 2 SM XTAL 2 4 1 1 2 C5D10 22 PF 5% 50 V NPO 402 C18 C19 BKUP_SB_SYNC_CLKP BKUP_SB_SYNC_CLKN IN IN R5D11 1 0 OHM 2 SMC_XTAL_OUT_R 5% 402 CH PEX_REF_CLK1_REQN PEX_REF_CLK2_REQN SMC_RST_N_OUT F22 V12P0_PWRGD OUT 1 CLK_MONITOR E17 SB_CLK_MONITOR E18 E19 100M_SYNC_CLK_BYPASS_DP 100M_SYNC_CLK_BYPASS_DP RTC_CLK_OUT A21 RTC_CLK_OUT A18 A19 XTAL_CLK_OUT XTAL_CLK_IN EMMC_CLK ENET_REF_CLK 42 AF22SMC_RST_N_OUT_R I27 VPGM AD22 SMC_XTAL_OUT SMC_XTAL_IN 3 GND1 GND2 PEX_REF_CLK1_REQN PEX_REF_CLK2_REQN IN R5R17 100 KOHM 5% 2 EMPTY 402 R5D5 1 32 G21 V_EXT_DET V_VDD18_DET DB5D7 AD24 R5R18 1 2 SMC_BYPASS_CLK_IN D21 TEST SOC_NS_SYNC_CLK_DP SOC_NS_SYNC_CLK_DN SMC_BYPASS_CLK_IN 10 KOHM 5% 402 CH IN IN 1 1 DB5R2 DB5R3 IN IN SOC_NS_AV_CLK_DP SOC_NS_AV_CLK_DN 2 C5R15 1 UF 10% 16 V X5R 603 D R4D29 1 2 1 KOHM 1% CH 402 SMC_RST_N 1 1 2 OUT 65 26 42 OUT 8 C4D3 270 PF 10% 50 V X7R 402 R5D12 AC16 MMC_CLK C20 ENET_REF_CLK OUT 33 B16 SOC_REF_NS_100M_CLKP B17 SOC_REF_NS_100M_CLKN OUT OUT 2 2 A13 SOC_AV_NS_100M_CLKP A14 SOC_AV_NS_100M_CLKN OUT OUT 2 2 1 2 X32K_X1 0 OHM 5% CH 1 R5D13 402 69.8 KOHM 1% 2 EMPTY 402 R5B17 BKUP_SB_PEX_REF_CLKP BKUP_SB_PEX_REF_CLKN E20 D20 PCIE_BYPASS_CLK_DP PCIE_BYPASS_CLK_DN PEX_REF_CLK2_DP PEX_REF_CLK2_DN B20 SOC_NB_PEX_SS_100M_CLKP B21 SOC_NB_PEX_SS_100M_CLKN OUT OUT 2 2 250M_CLK_BYPASS_DP 250M_CLK_BYPASS_DN F20 F21 250M_CLK_BYPASS_DP 250M_CLK_BYPASS_DN PEX_REF_CLK1_DP PEX_REF_CLK1_DN C14 ENET_PEX_SS_100M_CLKP C15 ENET_PEX_SS_100M_CLKN OUT OUT 32 32 BKUP_SB_AV_CLKP BKUP_SB_AV_CLKN D16 D17 AV_CLK_BYPASS_DP AV_CLK_BYPASS_DN PEX_REF_CLK0_DP PEX_REF_CLK0_DN A15 SOC_PEX_SS_100M_CLKP A16 SOC_PEX_SS_100M_CLKN OUT OUT 2 2 X861949-001 DB5D4 1 BI R5D4 49.9 OHM 1% EMPTY 402 R5R20 11.3 KOHM 1% CH 402 R5R19 1.13 KOHM 1% CH 402 PEX_XTAL2 100 OHM 1% 402 EMPTY OUT 32 C BGA515 B B A A MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 29/72 2 CSA PAGE 29/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 43 IN V_VREG_12P0_TO_5P0_3P3 V_KIC1P8AUX V_SB1P8 1 2 KIC3P3HDMI_C 10 KOHM 1% EMPTY 402 Q6P1 1 60 OHM 0.5 A 0.1DCR D 1 I3 U4D2 2 2 FB 603 1 R6P7 1 2 10 KOHM 1% EMPTY 402 KIC3P3HDMI_B EMPTY 2 KIC 1 C5R7 2 U4D2 C5R14 4.7 UF 10% 6.3 V X5R 603 FB6R7 IC KIC AUX_VDD18[0] AUX_VDD18[1] AUX_VDD18[2] HDMI_VDD33[0] HDMI_VDD33[1] M5 M6 1 1 C 2 C6R74 4.7 UF 10% 6.3 V X5R 603 2 FB 603 1 2 C6R75 4.7 UF 10% 6.3 V X5R 603 H24 G23 G24 PLL2_VDD11S[0] PLL2_VDD11S[1] PLL2_VDD11S[2] 1 V_KIC3P3USB V_3P3STBY 1 60 OHM 0.5 A 0.1DCR AE10 AD10 AD11 2 FB 603 1 60 OHM 0.5 A 0.1DCR 1 C6R38 4.7 UF 10% 6.3 V X5R 603 2 F12 F13 E12 1 4.7 UF 10% 6.3 V X5R 603 2 1 VDD33S_XTAL[0] VDD33S_XTAL[1] VDD18S[0] VDD18S[1] VDD18S[2] VDD18S[3] VDD18S[4] VDD18S[5] FLSH_VDD18S[0] FLSH_VDD18S[1] FLSH_VDD18S[2] FLSH_VDD18S[3] F19 F17 AD26 AC24 AC25 W24 W25 W26 AD14 AD13 AD12 AE13 1 2 1 2 1 60 OHM 0.5 A 0.1DCR C6R69 4.7 UF 10% 6.3 V X5R 603 2 1 120 OHM 0.2A A 0.5DCR PLL1_VDD18 PLL0_VDD18 PLL1_VDD11 PLL0_VDD11 F15 F16 PEX_VDD11[0] PEX_VDD11[1] G26 F26 2 1 C6R73 2 2 FB 603 1 C5R4 4.7 UF 10% 6.3 V X5R 603 1 4.7 UF 10% 6.3 V X5R 603 2 PEX_VDD18[0] PEX_VDD18[1] 2 C5R5 4.7 UF 10% 6.3 V X5R 603 C V_SB1P1 FB5R4 1 120 OHM 0.2A A 0.5DCR C5R8 V_KIC1P8PLL0 1 60 OHM 0.5 A 0.1DCR 2 FB 603 C5R3 2 4.7 UF 10% 6.3 V X5R 603 FB5R1 4.7 UF 10% 6.3 V X5R 603 E14 E15 F24 E23 1 4.7 UF 10% 6.3 V X5R 603 2 FB 603 1 V_SB1P1 FB5R2 1 1 AD7 AC6 AA6 Y6 W6 USB3_VDD18<0> USB3_VDD18<1> USB3_VDD18<2> USB3_VDD18<3> USB3_VDD18<4> USB3_VDD11<0> USB3_VDD11<1> USB3_VDD11<2> USB3_VDD11<3> 2 FB 603 1 C5R10 4.7 UF 10% 6.3 V X5R 603 2 V6 U5 U6 T6 2 C5R11 4.7 UF 10% 6.3 V X5R 603 V_SB1P1 C5R2 B 4.7 UF 10% 6.3 V X5R 603 1 E2 E4 SATA_VDD18[0] SATA_VDD18[1] SATA_VDD11[0] SATA_VDD11[1] F6 E6 2 1 C6R89 10 UF 20% 6.3 V X5R 603 2 C6R90 4.7 UF 10% 6.3 V X5R 603 V_SB1P8 V_1P8STBY V_SB1P1 1 BGA515 1 C5R12 1 UF 10% 6.3 V X5R 402 2 V_SB1P1 C5R13 10 UF 20% 6.3 V X5R 603 C7 D7 DP_VDD18[0] DP_VDD18[1] DP_VDD11[0] DP_VDD11[1] DP_VDD11[2] E7 E8 F9 1 X861949-001 BGA515 2 1 C6R92 10 UF 20% 6.3 V X5R 603 V_SB1P1 FB6R2 A 1 2 1 60 OHM 0.5 A 0.1DCR C6R55 4.7 UF 10% 6.3 V X5R 603 2 FB 603 1 2 A C6R33 4.7 UF 10% 6.3 V X5R 603 1 2 MICROSOFT CONFIDENTIAL 6 5 2 C6P9 4.7 UF 10% 6.3 V X5R 603 V_KIC1P8USB V_SB1P8 7 C6P11 4.7 UF 10% 6.3 V X5R 603 V_KIC1P1PLL1 2 FB 603 C5R9 V_SB1P8 2 8 D V_KIC1P1PLL0 V_KIC1P8PLL1 1 60 OHM 0.5 A 0.1DCR FB6R4 V_1P8STBY HDMI_VDD11[0] HDMI_VDD11[1] HDMI_VDD11[2] P5 P6 N5 V_SB1P8 X861949-001 C6R93 C6R47 4.7 UF 10% 6.3 V X5R 603 V_KIC3P3XTAL V_3P3STBY I4 CK_VDD18[0] CK_VDD18[1] CK_VDD18[2] FB5R3 C6R15 4.7 UF 10% 6.3 V X5R 603 2 VDD11S[0] VDD11S[1] VDD11S[2] VDD11S[3] VDD11S[4] VDD11S[5] VDD11S[6] VDD11S[7] VDD11S[8] VDD11S[9] VDD11S[10] VDD11S[11] VDD11S[12] VDD11S[13] VDD11S[14] VDD11S[15] VDD11S[16] VDD11S[17] VDD11S[18] VDD11S[19] 2 FB 603 C6R66 V_SB1P8 V_1P1STBY B 2 FB6R1 2 T14 R12 R13 R14 R15 R16 P11 P13 P15 P16 N11 N12 N13 N14 N16 M12 M13 M15 L13 L14 R6P12 V_SB1P1 1 USB2_VDD33S[0] USB2_VDD33S[1] USB2_VDD33S[2] 2 FB 603 1 0 OHM 5% 2 EMPTY 402 KIC3P3HDMI_FB 4.7 UF 10% 6.3 V X5R 603 V_KIC1P8CK FB6R3 FB6R5 1 60 OHM 0.5 A 0.1DCR 11 of 11 E10 D9 D11 V_3P3STBY V_KIC1P1SPLL2 1 120 OHM 0.2A A 0.5DCR KIC3P3HDMI_G 2 AB15 AB17 AA15 AA16 AA17 W21 W22 W23 L6 K5 AO3414L FET Q6P2 3 1 V_KIC3P3HDMI 4.7 UF 10% 6.3 V X5R 603 V_SB1P8 VDD33S_1[0] VDD33S_1[1] VDD33S_1[2] VDD33S_1[3] VDD33S_1[4] VDD33S_1[5] VDD33S_1[6] VDD33S_1[7] VDD33S_2[0] VDD33S_2[1] 2 SOT23 10 KOHM 1% 2 CH 402 IC 10 of 11 V_1P1STBY R6P4 1 3 FB5R7 V_3P3 V_5P0 R6P11 4 3 1 C6P18 10 UF 20% 6.3 V X5R 603 PROJECT NAME PAGE GREYBULL_RETAIL 30/72 2 2 CSA PAGE 30/72 1 C6P17 4.7 UF 10% 6.3 V X5R 603 FAB REV M 1.0 8 7 6 5 4 3 2 1 KIC, DECOUPLING D D 1 C6R70 1 2 1 C6R24 2 1 C6R51 1 UF 10% 6.3 V X5R 402 C6R40 1 2 1 UF 10% 6.3 V X5R 402 C6R42 1 2 1 UF 10% 6.3 V X5R 402 1 1 UF 10% 6.3 V X5R 402 1 1 C6R31 2 1 1 C6R67 2 1 C6R30 1 2 C6R1 1 UF 10% 6.3 V X5R 402 C6R29 1 2 2 1 UF 10% 6.3 V X5R 402 1 C6R36 2 C6R37 2 1 UF 10% 6.3 V X5R 402 2 1 1 UF 10% 6.3 V X5R 402 C6R57 1 2 1 UF 10% 6.3 V X5R 402 C6R26 1 2 1 UF 10% 6.3 V X5R 402 C6R78 1 2 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 2 C6R19 2 1 C6R21 1 2 1 C6R11 C6R64 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 2 1 C6R82 2 2 1 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 C6R83 C6R86 C6R48 2 1 1 V_KIC1P8PLL1 V_KIC1P8PLL0 1 C6R54 2 1 UF 10% 6.3 V X5R 402 1 C6R49 2 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 C6R45 1 2 1 1 UF 10% 6.3 V X5R 402 C6R88 2 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 1 2 1 7 6 5 C6R18 C6R34 C6R39 2 1 C6R84 2 C6R14 C6R10 C 2 1 UF 10% 6.3 V X5R 402 V_SB1P8 C5R1 2 B 1 UF 10% 6.3 V X5R 402 2 V_KIC3P3HDMI 1 UF 10% 6.3 V X5R 402 C6R81 C6R79 1 UF 10% 6.3 V X5R 402 C6R80 1 2 1 1 2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 C6R77 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 C6R7 1 2 1 C6R5 C6R20 2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 2 1 C6R9 2 1 UF 10% 6.3 V X5R 402 2 V_KIC1P1PLL1 V_KIC1P1PLL0 2 1 UF 10% 6.3 V X5R 402 1 C6R62 1 2 C6R65 4 A 2 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 MICROSOFT CONFIDENTIAL 8 1 1 UF 10% 6.3 V X5R 402 C6R28 1 2 1 1 UF 10% 6.3 V X5R 402 1 2 1 UF 10% 6.3 V X5R 402 C6R17 1 2 1 UF 10% 6.3 V X5R 402 1 C6R16 1 UF 10% 6.3 V X5R 402 V_KIC3P3USB V_SB1P8 1 UF 10% 6.3 V X5R 402 2 1 1 2 C6R87 2 V_KIC1P1SPLL2 1 UF 10% 6.3 V X5R 402 V_SB1P1 1 C6R63 1 UF 10% 6.3 V X5R 402 2 1 1 UF 10% 6.3 V X5R 402 C6R46 1 2 C6R27 V_SB1P1 1 UF 10% 6.3 V X5R 402 C6R72 1 2 1 UF 10% 6.3 V X5R 402 V_KIC1P8CK C6R52 1 2 1 UF 10% 6.3 V X5R 402 C6R6 1 2 1 V_SB1P1 C6R22 1 UF 10% 6.3 V X5R 402 C6R85 1 2 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 C6R23 1 2 1 2 C6R12 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 1 C6R43 1 UF 10% 6.3 V X5R 402 C6R44 1 2 1 1 UF 10% 6.3 V X5R 402 V_KIC3P3XTAL V_KIC1P8USB 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 C6R25 1 2 C6R8 1 2 1 UF 10% 6.3 V X5R 402 C6R71 1 2 A 2 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 C6R41 1 2 C6R60 C6R76 1 2 1 C6R13 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 1 2 1 UF 10% 6.3 V X5R 402 1 2 C6R4 V_1P8STBY 1 UF 10% 6.3 V X5R 402 1 2 1 UF 10% 6.3 V X5R 402 C6R2 1 2 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 C6R32 1 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 B C6R68 C5R6 4.7 UF 10% 6.3 V X5R 603 2 4.7 UF 10% 6.3 V X5R 603 C6R53 1 2 C6R61 1 2 1 UF 10% 6.3 V X5R 402 4.7 UF 10% 6.3 V X5R 603 C C6R59 V_3P3STBY V_SB1P1 V_KIC1P8AUX V_1P1STBY 3 PROJECT NAME PAGE GREYBULL_RETAIL 31/72 2 CSA PAGE 31/72 1 FAB REV M 1.0 8 7 6 5 4 01.10 A V_3P3STBY_ENET 10 KOHM 5% 2 CH 402 R5B15 26 1 2 10 KOHM 5% CH 402 OUT IN IN 29 29 2 29 V_3P3 OUT OUT OUT PEX_ENET_SOC_TN_C 1 V_3P3STBY_ENET 6.3 V 10% 402 X5R 0.1 UF 1 26 1 1 15 KOHM 1% 2 EMPTY 402 FT6N2 FTP 5 ENET_V_3P3STBY_EN IN R6N2 4 EMPTY 1206 U4B5 IC TPS2065 IN EN OUT 1 OC_N 3 GND 2 V_3P3STBY_ENET 1 V_3P3STBY_ENET_FLT_N 2 X862402-001 SOT23-5 10 KOHM 5% 2 CH 402 1 1 1 C4B6 10 UF 20% 6.3 V X5R 603 1 2 D IN IN IC RTL8151GNM ENET_WAKE_N ENET_ISOLATE_N 28 26 LANWAKEB ISOLATEB DVDD33_1 DVDD33_2 27 39 ENET_PEX_SS_100M_CLKP ENET_PEX_SS_100M_CLKN PEX_ENET_SOC_TP PEX_ENET_SOC_TN PEX_SOC_ENET_TP_C PEX_SOC_ENET_TN_C 19 20 22 23 17 18 25 16 REFCLK_P REFCLK_N HSOP HSON HSIP HSIN PERSTB CLKREQB DVDD10_1 DVDD10_2 DVDD10_3 13 29 41 AVDD10_1 AVDD10_2 AVDD10_3 AVDD10_4 3 6 9 45 43 44 CKXTAL1 CKXTAL2 EVDD10 21 36 33 34 35 46 REGOUT ENSWREG VDDREG1 VDDREG2 RSET AVDD33_1 AVDD33_2 AVDD33_3 AVDD33_4 12 42 47 48 32 30 EEDI/SDA EECS/SCL 40 37 31 LED0 LED1/EESK LED2/EEDO MDIP0 MDIN0 MDIP1 MDIN1 MDIP2 MDIN2 MDIP3 MDIN3 1 2 4 5 7 8 10 11 14 15 38 NC SMBDATA GPO GND1 GND2 24 49 X862048-001 ENET_RST_N PEX_REF_CLK1_REQN PEX_XTAL1 PEX_XTAL2 49.9 OHM 1% CH 402 0 OHM 5% CH 402 Y5B1 25 MHZ PEX_XTAL_1_R 1 3 GND1 GND2 2 4 PEX_XTAL_2_R R5B8 C5B5 18 PF 5% 50 V NPO 402 1 2 2 0.1 UF 10% 10 V X5R 402 IND SM C5B7 ENET_RSET 4.7 UF 10% 6.3 V X5R 805 1 C5B4 18 PF 5% 50 V NPO 402 2 C5N17 1 C5N15 4.7 UF 10% 6.3 V X5R 805 R5B6 2.49 KOHM 1% 2 CH 402 V_3P3STBY_ENET 1 SM XTAL 1 C5B9 4.7 UH 0.9 A 0.2 OHM ENET_REGOUT 2 0.1 UF 10% 10 V X5R 402 71 OUT FT5N3 FTP 71 OUT FT5N4 FTP 71 OUT FT5N5 FTP 71 IN FT5N6 FTP ENET_EEDI 1 ENET_SMBCLK R5B7 B 1L5B12 V_1P0STBY ENET_EECS 1 ENET_EESK ENET_SMBDATA IN 1 C5N9 0.1 UF 10% 6.3 V X5R 402 2 1 2 1 0.1 UF 10% 6.3 V 2 X5R 402 C5N16 1 C5N1 0.1 UF 10% 6.3 V 2 X5R 402 C5N6 1 0.1 UF 10% 6.3 V 2 X5R 402 C5N2 1 0.1 UF 10% 6.3 V X5R 402 2 C5N10 0.1 UF 10% 6.3 V X5R 402 V_1P0STBY 1 1 2 C5N11 1 0.1 UF 10% 6.3 V 2 X5R 402 1 0.1 UF 10% 6.3 V 2 X5R 402 C5N7 C5N14 1 0.1 UF 10% 6.3 V 2 X5R 402 MDIP0 MDIN0 MDIP1 MDIN1 MDIP2 MDIN2 MDIP3 MDIN3 C5N5 BI BI BI BI BI BI BI BI 1 UF 10% 6.3 V X5R 402 0.1 UF 10% 6.3 V 2 X5R 402 1 0.1 UF 10% 6.3 V 2 X5R 402 C5N3 0.1 UF 10% 6.3 V X5R 402 34 34 34 34 34 34 34 34 QFN49 B V_3P3STBY_ENET R5B9 2 1 ENET_EEDO 1 R5N1 10 KOHM 10 KOHM 5% 5% 2 EMPTY 2 EMPTY 402 402 DB5B1 2 4 ENET_LED0 1 3 ENET_LED1 EMPTY YELLOW-GREEN SM DB5B2 1 1 R5B11 1 2 V_3P3STBY ENET_LED0_R D5B1 2 R5B3 R4B16 1 2 0 OHM 5% EMPTY 1210 R5B5 2 1 1 1 KOHM 5% 402 EMPTY R5B12 2 1 511 OHM 1% 402 EMPTY ENET_LED3 GREEN EMPTY DB5B3 SM 1 10 KOHM 5% 2 EMPTY 402 1 R5B14 1 2 511 OHM 1% 402 EMPTY A R5B4 EEPROM CONFIG (93C66) GREYBULL WITH EEPROM GREYBULL W/O EEPROM CHIPSET RTL8151GNM STUFF STUFF R5B3 STUFF RTL8151GNM EMPTY EMPTY EMPTY U5B1 C5B3 MICROSOFT CONFIDENTIAL 6 V_3P3STBY_ENET 1 2 1 KOHM 5% 402 EMPTY 511 OHM 1% 402 EMPTY D5B2 7 0.1 UF 10% 6.3 V 2 X5R 402 1 FT5N7 FTP 8 2 C5N12 1 C5N13 1 C5N4 C FTP FT5N8 1 KOHM 5% 402 EMPTY V_3P3STBY_ENET 1 1 C5N8 0.1 UF 10% 6.3 V X5R 402 1 R5N2 A C6N1 0.1 UF 10% V 2 6.3 X5R 402 DB4B8 1 29 1 C4B5 10 UF 20% 6.3 V X5R 603 V_3P3STBY_ENET R5B16 2 2 26 R5N3 R5B13 10 KOHM 5% 2 CH 402 C R5P1 U5B2 10 KOHM 5% 2 EMPTY 402 IN 1 1 FT5N9 FTP 6.3 V 10% 402 X5R 0.1 UF 2 C6N2 0.1 UF 10% 6.3 V 2 X5R 402 1 KOHM 5% 2 CH 402 C5B6 1 2 PEX_ENET_SOC_TP_C C5B8 2 1 1 ENET_SMBALERT_N D R5B2 2 RT4B1 1 2 V_3P3STBY CONTROLLER, ETHERNET V_3P3STBY_ENET 1 3 5 4 3 R5B4 EMPTY R5N2 STUFF EMPTY EMPTY PROJECT NAME PAGE GREYBULL_RETAIL 32/72 2 R5B9 R5B5 R5N1 EMPTY EMPTY EMPTY EMPTY CSA PAGE 32/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 V_1P8STBY EMMC CH 1 402 R4D15 R4D21 R4D23 402 33 33 33 MMC_DATA<7> BI MMC_DATA<6> BI MMC_DATA<5> BI MMC_DATA<4> BI MMC_DATA<3> BI MMC_DATA<2> BI MMC_DATA<1> 33 BI MMC_DATA<0> 33 BI MMC_CMD BI MMC_CLK 33 C BI 33 33 33 29 33 1 2 0 OHM 5% CH 402 B R4D18 R4D16 1 2 0 OHM 5% CH 402 1 2 0 OHM 5% CH 402 1 2 0 OHM 5% CH 402 X861949-001 1% 1 2 0 OHM 5% CH 402 1 2 0 OHM 5% CH 402 I446 AE18 AD15 AE15 AD16 AF16 AF18 AD17 AE17 MMC_RST_N_R 1 KOHM 5% 402 CH DB3D3 FT7R1 FTP W5 CMD MMC_CLK_R W6 CLK U5 RSTN 1 1 AE14 MMC_RST_N 33 OUT 33 FTP MMC_X6 MMC_X4 MMC_X8 MMC_X5 D3 D5 D7 SIGNALS ROUTED TO NC PINS FOR ESCAPE A PIN PIN PIN PIN PIN J6 J5 J4 J3 J2 ROUTED ROUTED ROUTED ROUTED ROUTED TO TO TO TO TO PIN PIN PIN PIN PIN K7, K8 K5 K3, L3 H2 K1 VDDI PIN K2 ROUTED TO PIN L1 U9 T10 N5 M6 VDDI K2 GND PIN Y2 ROUTED TO PIN W1 A4 A6 A9 A11 B2 B13 D1 D14 H1 H2 H8 H9 H10 H11 H12 H13 H14 J1 J7 J8 J9 J10 J11 J12 J13 J14 K1 K3 K7 K8 K9 K10 K11 K12 K13 5 4 2 1 C7R6 0.1 UF 10% 6.3 V X5R 402 2 C7R5 2.2 UF 20% 6.3 V X5R 402 1 2 C7R9 1 C6R50 1 C6R58 1 UF 10% 6.3 V X5R 402 2 0.1 UF 10% 6.3 V X5R 402 0.1 UF 10% 6.3 V X5R 402 2 1 2 C6R56 2.2 UF 20% 6.3 V X5R 402 2 1 C7R7 0.1 UF 10% 6.3 V X5R 402 2 C7R8 2.2 UF 20% 6.3 V X5R 402 C VDDI_ROUTE AA6 AA4 Y5 Y2 K4 U8 R10 P5 M7 1 2 C3D9 1 UF 10% 6.3 V X5R 402 MMC_X NETS ARE DUMMY NETS TO IMPROVE PAD ADHESION NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC25 NC26 NC27 NC28 NC29 NC30 NC31 NC32 NC33 NC34 NC35 NC36 NC37 NC38 NC39 NC40 NC41 NC42 NC43 NC44 NC45 NC46 NC47 NC48 NC49 NC50 NC51 NC52 NC53 NC54 NC55 NC56 NC57 NC58 NC59 NC60 NC61 NC62 NC63 NC64 NC65 NC66 NC67 NC68 NC69 U3D1 K14 L1 L2 L3 D5 L4 L12 L13 L14 M1 M2 M3 M12 M13 M14 N1 N2 N3 N12 N13 N14 P1 P2 P12 P13 P14 R1 R2 R3 R12 R13 R14 T1 T2 T3 T12 AA7 AA10 H6 H7 D6 K5 M5 M8 M9 M10 N10 P3 P10 R5 T5 U6 U7 U10 DB633 DB634 T13 DB637 DB635 DB636 DB638T14 U1 U2 U3 U12 U13 U14 V1 V2 V3 V12 V13 V14 W1 W2 W3 BGA169B MICROSOFT 6 0.1 UF 10% 6.3 V X5R 402 V_3P3STBY DRAWING Tue Jun 18 16:42:22 2013 CONFIDENTIAL 7 2 1 C3D8 IC X866676-001 [PAGE_TITLE=EMMC] 8 VCC3 VCC2 VCC1 VCC0 eMMC_169PIN 2 of 3 1 BGA515 D7 D6 D5 D4 D3 AA5 AA3 Y4 W4 K6 0.1 UF 10% 6.3 V X5R 402 BGA169B U3D1 MMC_X7 D4 OUT VCCQ3 VCCQ2 VCCQ1 VCCQ0 VSSQ4 VSSQ3 VSSQ2 VSSQ1 VSSQ0 VSS3 VSS2 VSS1 VSS0 X866676-001 7 6 5 4 3 2 1 0 AF14 MMC_CMD DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 MMC_CMD_R 33 BI J6 J5 J4 J3 J2 H5 H4 H3 R4D24 R4D6 2 1 R4D36 10 KOHM 1% 402 CH 1/16W X806693-001 1 C7R4 1 R4D2 1 2 0 OHM 5% CH 402 R4D7 MMC_DATA_R<7> MMC_DATA_R<6> MMC_DATA_R<5> MMC_DATA_R<4> MMC_DATA_R<3> MMC_DATA_R<2> MMC_DATA_R<1> MMC_DATA_R<0> R4D20 R4D8 1 2 0 OHM 5% CH 402 2 R4D22 1 2 0 OHM 5% CH 402 emmc_169pin 1 of 3 VCCQ4 10 KOHM 1 2 0 OHM 5% CH 402 R4D12 MMC_DATA<7..0> MMC_DATA7 MMC_DATA6 MMC_DATA5 MMC_DATA4 MMC_DATA3 MMC_DATA2 MMC_DATA1 MMC_DATA0 MMC_RESET_N 2 CH IC U3D1 1% FT7R2 IC MMC_CMD 2 10 KOHM R4D14 10 KOHM 1% 2 EMPTY 402 KIC 5 of 12 2 CH 1 1 U4D2 10 KOHM R4D10 MMC_RST_N BI 1 10 KOHM 1% CH 1 10 KOHM 1% 2 1 402 10 KOHM 1% 2 CH 1 D V_1P8STBY 1% 2 1 402 R4D19 2 CH 402 V_1P8STBY 10 KOHM 1% CH 1 10 KOHM 1% 2 CH 402 R4D17 MEM,SM,8GB,FLASH,EMMC 1 1 402 R4D11 2 1 402 R4D13 MEM,SM,8GB,FLASH,EMMC I477 1 1 10 KOHM BOM PROPERTY 1% 1 R4D9 D 2 CH TRUEDESCR. EMMC_TOSH TRUE EMMC_SEC TRUE EMMC_HX MEM,SM,8GB,FLASH,EMMC 1 1 402 MATL REF_DES X866677-001 IC X875870-001 IC X867925-001 IC 1 R4D4 MS_PART# U3D1 U3D1 U3D1 3 IC eMMC_169PIN 3 of 3 RFU0 RFU1 RFU2 RFU3 RFU4 RFU5 RFU6 RFU7 RFU8 RFU9 RFU10 RFU11 RFU12 RFU13 RFU14 RFU15 RFU16 NC87 NC88 NC89 NC90 NC91 NC92 NC93 NC94 NC95 NC96 NC97 NC98 NC99 NC100 NC101 NC102 NC103 NC104 NC105 NC106 NC107 NC108 NC109 NC110 NC111 NC112 NC113 NC114 NC115 NC116 NC117 NC118 NC119 NC120 NC121 NC70 NC71 NC72 NC73 NC74 NC75 NC76 NC77 NC78 NC79 NC80 NC81 NC82 NC83 NC84 NC85 NC86 X866676-001 B MMC_X11 MMC_X3 MMC_X10 MMC_X12 MMC_X2 MMC_X1 A BGA169B PROJECT NAME PAGE GREYBULL_RETAIL 33/72 2 W7 W8 W9 W10 W11 W12 W13 W14 Y1 Y3 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 AA1 AA2 AA8 AA9 AA11 AA12 AA13 AA14 AE1 AE14 AG2 AG13 AH4 AH6 AH9 AH11 CSA PAGE 33/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 CONN, RJ45 + TOSLINK V_5P0 D D 1 2 IN C 1 2 34 32 34 32 BI BI MDIP1 MDIN1 3 4 TRD2_P TRD2_N 34 32 34 32 BI BI MDIP2 MDIN2 7 8 TRD3_P TRD3_N 34 32 34 32 BI BI MDIP3 MDIN3 9 10 TRD4_P TRD4_N RJ45_CT1 2 5 6 C5B2 C8A1 22 PF 5% 50 V NPO 402 EG8A1 X882235-001 45 6 7 EMPTY 402 TRD1_P TRD1_N CT1 CT2 CONN TOSLINK VCC VIN GND EMI1 EMI2 EMI3 EMI4 X866874-003 TH C SHLD1 SHLD2 11 12 X866473-004 TH 0.01 UF 10% 16 V X7R 402 EG5B5 EMPTY SP3010 EG5B4 EMPTY SP3010 B 2 3 1 2 MDIP0 MDIN0 1 2 CONN J5A1 RJ45 10P BI BI J8A2 SPDIF_OUT 1 34 32 34 32 1 UF 10% 6.3 V X5R 402 1 2 C8A4 34 32 34 32 BI BI MDIN3 MDIN3 1 10 D1A D1B 34 32 34 32 BI BI MDIN1 MDIN1 1 10 D1A D1B 34 32 34 32 BI BI MDIP3 MDIP3 2 9 D2A D2B 34 32 34 32 BI BI MDIP1 MDIP1 2 9 D2A D2B 34 32 34 32 BI BI MDIN2 MDIN2 4 7 D3A D3B 34 32 34 32 BI BI MDIN0 MDIN0 4 7 D3A D3B 34 32 34 32 BI BI MDIP2 MDIP2 5 6 D4A D4B 34 32 34 32 BI BI MDIP0 MDIP0 5 6 D4A D4B GNDA GNDB 3 8 B 3 8 GNDA GNDB CONNECT As TO Bs CONNECT As TO Bs X863136-001 DFN10 X863136-001 DFN10 A A MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 34/72 2 CSA PAGE 34/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 CONN, USB EG7B1 ESD ARRAY SP3011 D 8 7 24 35 24 35 BI BI USB3_BP_P0_RN USB3_BP_P0_RN 24 35 24 35 BI BI USB3_BP_P0_RP USB3_BP_P0_RP 9 6 D2A D2B 35 24 35 24 BI BI USB2_BP_P0_DN USB2_BP_P0_DN 11 4 D3A D3B 35 24 35 24 BI BI USB2_BP_P0_DP USB2_BP_P0_DP 12 3 D4A D4B 24 35 24 35 BI BI USB3_BP_P1_RN USB3_BP_P1_RN 13 2 D5A D5B 24 35 24 35 BI BI USB3_BP_P1_RP USB3_BP_P1_RP 14 1 D6A D6B V_5P0DUAL D RT7A1 1 2 D1A D1B V_5P0_USB3_P0 1 C7B1 01.50 A THRMSTR 1812 2 GNDA GNDB 10 5 2 220 UF 20% 10 V ELEC RDL 1 2 C7A2 470 PF 5% 50 V X7R 402 1 C7A1 4.7 UF 10% 6.3 V X5R 603 BOTTOM SLOT USB2_BP_P0_DN USB2_BP_P0_DP 35 24 35 24 BI BI 24 35 OUT USB3_BP_P0_RN 24 35 OUT USB3_BP_P0_RP USB3_BP_P0_TN_CMC USB3_BP_P0_TP_CMC 1 2 3 4 5 6 7 8 9 CM7B4 CONNECT As TO Bs C 24 X863137-001 DFN14 EG7B2 ESD ARRAY SP3011 USB3_BP_P0_TN 4 IN J7A2 CONN USB3 DUAL VBUS DD+ GND STDA_SSRX_N STDA_SSRX_P GND_DRAIN STDA_SSTX_N STDA_SSTX_P MTH1 MTH2 19 20 X865822-004 TH 3 C CHK 24 USB3_BP_P0_TP 1 IN 2 80 OHM SM X869713-001 V_5P0DUAL BI BI USB3_BP_P1_TN_CMC USB3_BP_P1_TN_CMC 8 7 D1A D1B 35 35 BI BI USB3_BP_P1_TP_CMC USB3_BP_P1_TP_CMC 9 6 D2A D2B 35 24 35 24 BI BI USB2_BP_P1_DN USB2_BP_P1_DN 11 4 D3A D3B 35 35 BI BI USB2_BP_P1_DP USB2_BP_P1_DP 12 3 35 35 BI BI USB3_BP_P0_TN_CMC USB3_BP_P0_TN_CMC 13 2 D5A D5B 35 35 BI BI USB3_BP_P0_TP_CMC USB3_BP_P0_TP_CMC 14 1 D6A D6B 35 24 35 24 B RT7B2 1 2 01.50 A THRMSTR 1812 2 D4A D4B GNDA GNDB 10 5 220 UF 20% 10 V ELEC RDL 1 2 C7B3 470 PF 5% 50 V X7R 402 1 C7B2 4.7 UF 10% 6.3 V X5R 603 TOP SLOT USB2_BP_P1_DN USB2_BP_P1_DP 35 24 35 24 BI BI 24 35 OUT USB3_BP_P1_RN 24 35 OUT USB3_BP_P1_RP 24 BI BI 8 7 D1A D1B 24 35 24 35 BI BI USB3_FP_P0_RP USB3_FP_P0_RP 9 6 D2A D2B 35 24 35 24 BI BI USB2_FP_P0_DP USB2_FP_P0_DP 11 4 D3A D3B 35 24 35 24 BI BI USB2_FP_P0_DN USB2_FP_P0_DN 12 3 D4A D4B 35 35 BI BI USB3_FP_P0_TN_CMC USB3_FP_P0_TN_CMC 13 2 D5A D5B 35 35 BI BI USB3_FP_P0_TP_CMC USB3_FP_P0_TP_CMC 14 1 D6A D6B IN USB3_BP_P1_TN 4 IN USB3_BP_P1_TP 1 CONN J7A2 USB3 DUAL VBUS DD+ GND STDA_SSRX_N STDA_SSRX_P GND_DRAIN STDA_SSTX_N STDA_SSTX_P 01.50 A X865822-004 TH 3 35 24 35 24 GNDA GNDB BI BI 2 1 C3F1 2 2 1 220 UF 20% 10 V ELEC RDL C3F2 470 PF 5% 50 V X7R 402 2 1 C3F3 4.7 UF 10% 6.3 V X5R 603 USB2_FP_P0_DN USB2_FP_P0_DP 24 35 OUT USB3_FP_P0_RN 24 35 OUT USB3_FP_P0_RP USB3_FP_P0_TN_CMC USB3_FP_P0_TP_CMC 10 5 CM3F1 24 IN USB3_FP_P0_TN 4 24 IN USB3_FP_P0_TP 1 1 2 3 4 5 6 7 8 9 CONN J3F2 USB3_9P_2MH VBUS DD+ GND STDA_SSRX_N STDA_SSRX_P GND_DRAIN STDA_SSTX_N STDA_SSTX_P A MTH1 MTH2 10 11 X866825-003 TH 3 CHK 2 80 OHM SM X869713-001 MICROSOFT CONFIDENTIAL 6 21 22 V_5P0_USB3_FP THRMSTR 1812 CONNECT As TO Bs 7 MTH1 MTH2 80 OHM SM X869713-001 RT3F1 1 2 X863137-001 DFN14 8 B CHK 24 V_5P0DUAL EG3F1 ESD ARRAY SP3011 USB3_FP_P0_RN USB3_FP_P0_RN 10 11 12 13 14 15 16 17 18 CM7B3 CONNECT As TO Bs A 2 USB3_BP_P1_TN_CMC USB3_BP_P1_TP_CMC X863137-001 DFN14 24 35 24 35 V_5P0_USB3_P1 1 C7B4 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 35/72 2 CSA PAGE 35/72 1 FAB REV M 1.0 8 7 6 5 3 2 1 CONN, USB EG6B1 ESD ARRAY SP3011 D 4 D V_3P3STBY 24 36 24 36 BI BI USB3_AUX_RN USB3_AUX_RN 8 7 D1A D1B 24 36 24 36 BI BI USB3_AUX_RP USB3_AUX_RP 9 6 D2A D2B 36 24 36 24 BI BI USB2_AUX_DP USB2_AUX_DP 11 4 D3A D3B 402 DIO 36 24 36 24 BI BI USB2_AUX_DN USB2_AUX_DN 12 3 D4A D4B X882235-001 EG3B3 36 36 BI BI USB3_AUX_TN_CMC USB3_AUX_TN_CMC 13 2 D5A D5B 36 36 BI BI USB3_AUX_TP_CMC USB3_AUX_TP_CMC 14 1 D6A D6B 10 5 24 24 24 24 26 CONNECT As TO Bs 26 5 IN 4 EN R6B3 1 OC_N 3 GND 2 V_5P0_USB3_AUX_FLT 1 2 1 1 1 C4B9 22 UF 20% 6.3 V X7R 805 3P3V2 3P3V1 NETW_DP NETW_DN ACC_DP ACC_DN RESETN GND SHLD2 SHLD1 SHLD_ALL 1 R3B5 6 10 2 5 C TH 10 KOHM 5% 2 EMPTY 402 DB6B3 X862402-001 SOT23-5 100 KOHM 5% 2 CH 402 1 OUT DIO 402 2 1 UF 10% 6.3 V X5R 402 DIO 402 EG3B2 X882235-001 1 2 0 OHM 5% CH 603 J3B1 WIFI_HDR 11 1 7 8 3 4 9 2 C6B6 1 FT4N3 FTP EG3B1 X882235-001 01.50 A EMPTY 1812 U6B2 IC TPS2065 USB_AUX_EN IN 2 USB2_WIFI_DP USB2_WIFI_DN USB2_ACC_DP USB2_ACC_DN WIFI_RESET_N BI BI BI BI IN C4B10 1 UF 10% 6.3 V X5R 402 RT6B1 1 2 V_5P0DUAL 2 402 DIO X882235-001 EG3B4 1 GNDA GNDB X863137-001 DFN14 1 2 1 C R4B12 V_3P3STBY_BAJA V_5P0_USB3_AUX 2 1 B OUT 1 2 1 C6B4 4.7 UF 10% 6.3 V X5R 603 B I90 IC DIO 402 IR_BLAST_SENSOR_SIG IN USB2_AUX_DP USB2_AUX_DN BI BI 1 VBUS 8 IR_I/O 2 3 12 13 USB3_AUX_RP 36 24 36 2 C6B1 470 PF 5% 50 V X7R 402 36 USB3_AUX_TP_CMC USB3_AUX_TN_CMC 9 10 VCC GND_DRAIN D+ GND DGND GND STDA_SSRX_P STDA_SSRX_N MTH4 MTH3 STDA_SSTX_P MTH2 STDA_SSTX_N MTH1 TPS2590 5 V12P0_AUX 1 11 6 7 4 2 A 24 1 C6B3 4.7 UF 10% 16 V X5R 805 2 C6B2 1 UF 10% 16 V X5R 603 17 16 15 14 USB3_AUX_RN X862297-003 TH IN USB3_AUX_TP 1 2 IN USB3_AUX_TN 4 3 12 11 10 VOUT3 VOUT2 VOUT1 15 FLT_N 5 13 14 17 V_SOC1P8 CM6B2 24 1 GND1 GND2 GND3 MPAD VIN4 VIN3 VIN2 VIN1 4 3 2 1 ILIM 7 USB_AUX_OCP_ILIM IFLT 8 USB_AUX_OCP_IFLT CT 9 USB_AUX_OCP_CT 6 16 USB_AUX_OCP_RTRY_N RTRY_N EN_N 26 OUT R4N2 ON ILIM SETS LIMIT CURRENT: 3.1 A R4N1 ON IFLT SETS FAULT CURRENT: 3.1 A USB_AUX_OCP_EN_N C4N1 ON CT SETS FAULT TIME: 22 MS V_SOC1P8 QFN16 X866681-001 1 R6B8 R6B1 10 KOHM 5% 2 CH 402 10 KOHM 5% 2 CH 402 80 OHM SM X869713-001 V_12P0 U6B1 CONN J6A1 USB_13P_4MH 36 24 36 24 OUT 2 220 UF 20% 10 V ELEC RDL EG6B2 X882235-001 63 24 36 1 C6B5 USB_AUX_EN_D USB_AUX_OCP_FLT_N 1 R6B2 0 OHM 5% 2 CH 402 1 26 7 6 5 2 C4N1 1 R4N1 64.9 KOHM 1 R4N2 64.9 KOHM .68 UF 1% 10% 1% 6.3 V 2 CH 2 CH X5R 603 402 402 A 3 IN 1 USB_AUX_EN Q6B2 FET AO3414L 2 SOT23 MICROSOFT CONFIDENTIAL 8 1 R6B9 0 OHM 5% 2 EMPTY 402 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 36/72 2 CSA PAGE 36/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 EG7B3 ESD ARRAY SP3010 CONN, HDMI IN D 25 OUT 25 OUT 25 OUT 25 OUT 25 OUT 25 OUT 25 OUT 25 OUT 1 TMDS_RX_DP2 TMDS_RX_DN2 1 10 D1A D1B 2 9 D2A D2B 4 7 D3A D3B 5 6 D4A D4B TMDS_RX_DP1 TMDS_RX_DN1 TMDS_RX_DP0 TMDS_RX_DN0 D GNDA GNDB 3 8 CONNECT As TO Bs X863136-001 DFN10 TMDS_RX_CLKP TMDS_RX_CLKN C C 2 9 4 7 5 6 D2A D2B D3A D3B D4A D4B GNDA GNDB 1 10 25 38 BI HDMI_RX_CEC 3 8 B X863136-001 DFN10 R8B19 10 KOHM 1% 2 CH 402 CONNECT As TO Bs 1 EG7B4 ESD ARRAY SP3010 V_3P3STBY D1A D1B J7A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 TMDS_DATA2_DP TMDS_DATA2_SHD TMDS_DATA2_DN TMDS_DATA1_DP TMDS_DATA1_SHD TMDS_DATA1_DN TMDS_DATA0_DP TMDS_DATA0_SHD TMDS_DATA0_DN TMDS_CLK_DP TMDS_CLK_SHD TMDS_CLK_DN CEC RESERVED SCL SDA DDC_CEC_GND 5VCC HOT_PLUG_DET MT1 MT2 MT3 MT4 20 21 22 23 B HDMI_RX_DDC_5V_E X864613-003 3 HDMI_RX_DDC_5V_D 1 SOT-523 EMPTY R8B20 0 OHM 5% 2 CH 402 D8B3 1 1 OUT 2 26 CONN HDMI R8B21 DIO 402 HDMI_RX_DDC_5V 1 1 R8A2 100 KOHM 1% 2 CH 402 2 C8B1 0.1 UF 10% 6.3 V EMPTY 402 R8A3 EG7A7 X882235-001 DIO 402 HDMI_HPD_PIN 1 R3M2 47 KOHM 1% 2 CH 402 1 R8B9 1HDMI_RX_DDC_5V_G 1 2 10 KOHM 1% CH 603 EG7A9 X882235-001 1 R3M1 47 KOHM 1% 2 CH 402 2 U8B2 FET SOT23 2 2 3 1 2 KOHM 1% 2 EMPTY 402 2 1 SM 1 2 1 KOHM 5% CH 402 HDMI_RX_HPD IN 25 EG8A7 X882235-001 EMPTY 402 A A 2 1 BI EG7A3 X882235-001 EG7A4 X882235-001 DIO 402 DIO 402 2 BI 26 HDMI_RX_DDC_CLK HDMI_RX_DDC_DATA 1 26 MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 37/72 2 CSA PAGE 37/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 IN IN 2 TMDS_TX_DP2 TMDS_TX_DN2 1 2 1 2 TMDS_TX_DP2_C TMDS_TX_DN2_C 2 1 2 IN IN 2 TMDS_TX_DP0 TMDS_TX_DN0 1 2 1 4 7 D3A D3B 5 6 D4A D4B D1A D1B D2A D2B D3A D3B D4A D4B 2 9 4 7 5 6 C8B6 402 X5R 6.3 V 0.1 UF 10% 2 D2A D2B 1 10 EG8B2 ESD ARRAY SP3010 0.1 UF 10% 6.3 V X5R 402 C8B5 C 2 9 TMDS_TX_DP1_C TMDS_TX_DN1_C 2 CONNECT As TO Bs 1 X863136-001 DFN10 TMDS_TX_DP1 TMDS_TX_DN1 D1A D1B 3 8 IN IN 2 1 10 GNDA GNDB 2 ESD DIODE ARRAYS ARE INCLUDED FOR EVALUATION. TO BE CLEANED UP LATER. EG8B1 ESD ARRAY SP3010 0.1 UF 10% 6.3 V X5R 402 C8B4 C8B3 402 X5R 6.3 V 0.1 UF 10% D 1 CONN, HDMI OUT C8B2 402 X5R 6.3 V 0.1 UF 10% GNDA GNDB CONNECT As TO Bs J8A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 0.1 UF 10% 6.3 V X5R C8B8 402 402 C8B7 X5R 6.3 V 0.1 UF 10% 2 25 37 0.1 UF 10% 6.3 V X5R 402 C8B9 402 1% 2 CH 402 1 1 R1N4 2 KOHM 1% 2 CH 402 HDMI_DP_OUT_SEL 47.5 KOHM 1% 2 CH 402 FET REQURIEMENTS U2N1 0.1 UF 10% 25 V EMPTY 402 2 SOT23 X801032-001 26 R1N3 IN BI HDMI_TX_DDC_DATA VCCB VCCA HDMI_OUT_DDC_DATA 1 2 AUX VS DDX STUFFING MODE R9B8/R9B9 R9A5/R9A6 R9A3/R9A4 AUX 0.1 UF CAP STUFF EMPTY 26 7 6 SCLB SDAB SCLA SDAA 2 3 EN 5 GND 1 8 STUFF EMPTY 7 6 C2N1 1 UF 10% 6.3 V X5R 402 5 IN 1 R2N4 10 KOHM 5% 2 CH 402 EN 3 GND 2 X867973-001 SOT23-5 5 R1M3 HDMI_OUT_DDC_BUFF_CLK 1 2 22 OHM 5% CH 402 DIO 402 1 1 DB8B1 4 2 4.7 UF 10% 16 V X5R 805 3 R9B1 10 KOHM 1% 1 2 CH 402 DIO 402 3 DP0_HPD U9B2 FET OUT 2 26 SOT23 X857156-001 3 1 2 10 KOHM 1% CH 402 2 CH 402 DIO 402 1 HDMI_TX_HPD_G 1 R1N1 EG9B1 100 KOHM X882235-001 1% OUT C8A2 B V_3P3STBY EG9A1 X882235-001 R9B16 0.1 UF 10% 6.3 V EMPTY 402 V_5P0_HDMI_OUT 1 SM DIO 402 R9A8 1 2 22 OHM 5% CH 402 C9B13 1 2 HDMI_OUT_DDC_CLK_R V_3P3 0.1 UF 10% 1 R9A5 6.3 V 100 KOHM EMPTY 1 R9A6 5% 402 100 KOHM 2 EMPTY 5% 402 2 EMPTY 402 C9B15 1 2 HDMI_OUT_DDC_DATA_R V_5P0_HDMI_FLT_N 20 21 22 23 MT1 MT2 MT3 MT4 X864613-003 EG8A8 X882235-001 1 EG9A2 X882235-001 TMDS_DATA2_DP TMDS_DATA2_SHD TMDS_DATA2_DN TMDS_DATA1_DP TMDS_DATA1_SHD TMDS_DATA1_DN TMDS_DATA0_DP TMDS_DATA0_SHD TMDS_DATA0_DN TMDS_CLK_DP TMDS_CLK_SHD TMDS_CLK_DN CEC RESERVED SCL SDA DDC_CEC_GND 5VCC HOT_PLUG_DET 2 HDMI_OUT_DDC_BUFF_DATA EMPTY 1206 1 0.1 UF 10% 25 V X5R 402 R9A7 1 2 0 OHM 5% CH 402 OUT C9B3 2 KOHM 1% 2 CH 402 R9B4 FLT* 2 1 1 2 0 OHM 5% CH 402 IC U8B1 TPS2051C R1M4 2 KOHM 1% 2 CH 402 X871021-001 MSOP8 RT8A1 1 2 HDMI_V_5P0_EN 4 IN FT2N2 FTP 0 OHM RES 1 1 HDMI_OUT_DDC_CLK DDC 1 1 R9B5 26 01.10 A BI 8 4 HDMI_TX_DDC_CLK V_5P0DUAL 2 0.1 UF 10% 25 V X5R 402 2 KOHM 1% 2 CH 402 C8B19 FET 1 NEED TO BE ASSESSED. A 2 C1N1 V_5P0_HDMI_OUT C CONN HDMI HDMI_TX_HPD_D 1% 2 CH 1 R8B8 IN 2 402 1 R8B6 IC U1N1 PCA9507 38 2 1% 2 CH 1 2 HDMI_OUT_DDC_BUFF_EN 10 KOHM 5% 402 EMPTY V_5P0_HDMI_OUT IN 1 402 1 R8B4 38 1% 2 CH 402 HDMI_TX_HPD_PIN 1% 2 CH 1 R8B7 1% 2 CH 402 TMDS_COMMON_FET 3 1 R2N2 IN 1 R8B2 1 R8B5 1 1 PLACEHOLDER, ACTUAL 2 1% 2 CH 402 2 IN 1 R8B3 1 R2N3 1 47.5 KOHM 1% EMPTY 2 402 27 HDMI_TX_CEC 2 1% 2 CH 402 499 OHM 1 R8B1 499 OHM V_5P0DUAL FT2N1 FTP TO SB GPIO 1 2 0 OHM 5% CH 402 R8A1 499 OHM B HDMI_RX_CEC BI R1N2 499 OHM 1 TMDS_TX_CLKP_C TMDS_TX_CLKN_C 2 499 OHM IN 1 499 OHM 2 TMDS_TX_CLKP TMDS_TX_CLKN 499 OHM IN 499 OHM 2 3 8 X863136-001 DFN10 TMDS_TX_DP0_C TMDS_TX_DN0_C 2 D 1 2 U9B1 FET 2 SOT23 C9B1 0.1 UF 10% 6.3 V EMPTY 402 A 38 1 C8A3 0.1 UF 10% V 2 6.3 X5R 402 MICROSOFT PROJECT NAME PAGE CONFIDENTIAL GREYBULL_RETAIL 38/72 2 CSA PAGE 38/72 1 FAB REV M 1.0 25 7 4 3 V_3P3STBY D J4B2 1X5HDR2 HDD SATA 1 C5C7 2 SATA1_HDD_TN IN OUT 2 1 2 3 4 5 6 7 1 C5C13 1 4.7 UF 10% 6.3 V X5R 603 2 C5P4 2 1 UF 10% 6.3 V X5R 402 TH 3 V_12P0 C 1 SATA1_HDD_RP_C 1 C5C9 2 SATA1_HDD_RP 1 0.01 UF 10% 16 V X7R 402 2 U4C2 IC NCP45521 C4C3 VCC 1 UF 10% 16 V X7R 603 1 9 VIN1 VIN2 VOUT1 VOUT2 BLEED SR ODD SATA 25 B IN 25 IN SATA0_ODD_TP 26 1C4C172 0.01 UF 10% 16 V X7R 402 1C4C182 SATA0_ODD_TN 25 OUT 1C4C192 SATA0_ODD_RN 25 OUT SATA0_ODD_RP A SATA0_ODD_TN_C 2 1 2 26 HDD_PWR_EN IN FT5P1 FTP SATA0_ODD_RP_C 2 10 UF 10% 16 V EMPTY 805 1 2 1 1 R5C2 U5C4 IC MP5010B VCC SOURCE1 SOURCE2 SOURCE3 SOURCE4 SOURCE5 C5C25 10 KOHM 5% 2 CH 402 1 2 1 KOHM 1% CH 402 HDD_PWR_EN_R 10 UF 10% 16 V EMPTY 805 8 DV/DT EN/FLT ILIMIT NC GND C5C1 220 UF 20% 10 V 2 ELEC RDL 11 1 V_5P0_HDD 2 3 4 5 ODD_STATUS_R 1 2 100 OHM 1% CH 402 ODD_STATUS OUT 1 7 HDD_PWR_ILIMIT 6 10 ODD_OPEN 1 2 C5C17 75 PF 5% 50 V NPO 402 1 3 5 7 9 11 1 TH 2 7 C5C3 4.7 UF 10% 16 V X5R 805 6 1 2 C4C11 1 UF 10% 16 V X5R 603 2 1 1 IN IN IN 1 C5C14 1 C5P3 4.7 UF 10% 6.3 V X5R 603 2 1 UF 10% 6.3 V X5R 402 2 5 IC U5C1 MP5010B ODD_PWR_DVDT R5C12 ODD_3P3V_STBY_PULSE V_5P0_ODD V_12P0_ODD C5C24 39 39 39 26 ODD_PWR_EN IN FT5P2 FTP 1 1 R5C3 10 KOHM 5% 2 CH 402 1 UF 10% 6.3 V X5R 402 VCC SOURCE1 SOURCE2 SOURCE3 SOURCE4 SOURCE5 C5C16 270 PF 10% 50 V X7R 402 R5C1 1 2 1 KOHM 1% CH 402 ODD_PWR_EN_R 9 DV/DT 8 EN/FLT ILIMIT NC GND 2 11 1 V_5P0_ODD 2 3 4 5 7 ODD_PWR_ILIMIT 6 10 22 OHM 5% 2 CH 2 402 39 C5C12 10 UF 20% 6.3 V X5R 805 C5C2 1 UF 10% 6.3 V X5R 402 OUT 1 R5C4 22 OHM 5% 2 CH 402 1 2 39 A C5C11 10 UF 20% 6.3 V X5R 805 X878106-001 DFN11 MICROSOFT CONFIDENTIAL 4 1 V_5P0 2 4 6 8 10 12 R5C6 X878106-001 DFN11 26 100 KOHM 5% 2 CH 402 B OUT 1 1 R5C13 C V_5P0 270 PF 10% 50 V X7R 402 R5C5 39 C4C10 0.015 UF 10% 50 V X7R 603 9 TH 2 10 UF 10% 16 V X5R 805 C4C7 HDD_PWR_DVDT 8 10 UF 10% 16 V X5R 805 1 1 2 3 4 5 6 7 SATA0_ODD_RN_C C4C9 1 C6P4 1 C6P5 R5C14 ODD_WAKE_N 8 4 9 OUT IN 1 2 1 OUT 39 OUT ODD_PWR_SR X866665-001 DFN8 R6P3 ODD_3P3V_STBY_PULSE 1 UF 10% 6.3 V X5R 402 7 V_12P0_ODD 8 5 6 SOT23 X857156-001 C4C4 J4C1 1X7SATA J5C3 2X6HDR2 26 GND 2 3 10 KOHM 5% 2 EMPTY 402 100 KOHM 5% 2 CH 402 26 EN 0.01 UF 10% 16 V X7R 402 V_3P3STBY 1 2 ODD_PWR_EN 1 0.01 UF 10% 16 V X7R 402 1C4C202 IN SATA0_ODD_TP_C 0.01 UF 10% 16 V X7R 402 2 U5C2 FET 1 ODD_3P3V_STBY_EN IN V_5P0 SATA1_HDD_RN_C OUT R5C7 10 KOHM 5% 1 CH 402 TH 8 R5C8 0 OHM 5% 2 CH 402 26 0.01 UF 10% 16 V X7R 402 25 1 1 2 3 4 V_5P0_HDD IN 9 1 C5C8 2 SATA1_HDD_RN 39 J5C1 1X7SATA 0.01 UF 10% 16 V X7R 402 25 1 SATA1_HDD_TP_C SATA1_HDD_TN_C 25 2 CONN, ODD + HDD 0.01 UF 10% 16 V X7R 402 D 5 1 C5C6 2 SATA1_HDD_TP IN 6 ODD_3P3V_STBY_S 8 3 PROJECT NAME PAGE GREYBULL_RETAIL 39/72 2 CSA PAGE 39/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 CONN, LITHIUM + FAN D D V_3P3STBY CONN J5F1 LITHIUM CONN 12 1 2 1 C5F10 C5F15 470 PF 5% 50 V NPO 402 V_5P0DUAL R5F22 100 KOHM 5% 2 CH 402 100 UF 20% 16 V ELEC RDL IN BI SMBUS_CLK SMBUS_DATA 26 OUT BINDSW_N 26 OUT IR_DATA IN LED_NEXUS_R 26 67 OUT PWRSW_N 26 67 OUT EJECTSW_N 65 44 26 66 65 64 54 53 52 50 44 26 1 R5F23 1 100 KOHM 5% 2 CH 402 R5F25 100 KOHM 5% 2 CH 402 C 1 2 C5F12 470 PF 5% 50 V NPO 402 C5F11 100 UF 20% 16 V ELEC RDL 26 B 26 1 R5F21 100 KOHM 5% 2 CH 402 1 249 KOHM 1% 2 CH 402 R5F19 1 2 0 OHM 5% CH 402 BINDSW_N_R PWRSW_N_R 8 PWRSW_N EJECTSW_N_R 10 R5F24 2 IN FAN_PWM 100 UF 20% 16 V ELEC RDL 1 2 FAN_PWM_R 33 OHMS 1% CH 402 X866836-003 TH FAN_TACH_IN_R 1 2 3 4 R7B3 1 2 0 OHM 5% CH 402 FAN_TACH_IN OUT 1 2 TH A 27 C7B13 4700 PF 10% 16 V EMPTY 603 MICROSOFT CONFIDENTIAL 8 7 6 5 B 17 16 15 R7B2 J7C1 1X4HDR 26 SPARE3 SPARE2 SPARE1 4.7 KOHM 5% 2 CH 402 C7C1 R5R11 GND1 GND2 INT_N MTH1 MTH2 V_3P3 1 A LED_HALO LED_ZONE 9 14 11 18 19 R5F32 C EJECTSW_N 2 3 V_12P0 1 UF 10% 16 V X5R 603 V5P0_DUAL BINDSW_N LED_NEXUS 100 KOHM 5% 2 CH 402 C7B14 4 13 IR_DATA 1 2 10 KOHM 1% CH 402 1 1 I2C_CLK I2C_DATA 1 R5F26 1 2 10 KOHM 1% CH 402 5 6 7 INT_N OUT V_3P3STBY R5F20 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 40/72 2 CSA PAGE 40/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 CONN, PWR D D C C V_12P0 1 C9B11 2 26 470 UF 20% 16 V POLY TH 1 C9B6 1 2 2 470 UF 20% 16 V POLY TH C1N4 0.1 UF 10% 25 V X7R 603 1 2 C1N3 0.1 UF 10% 25 V X7R 603 2 IN V_5P0STBY 2 1 C9B5 220 UF 20% 10 V 2 ELEC RDL 1 2 C1N5 0.1 UF 10% 25 V X7R 603 R9A2 PSU_V12P0_EN 1 R9B2 B 1 10 KOHM 5% CH 402 1 2 100 OHM 1% CH 402 1 2 1 2 3 4 5 6 7 8 9 10 C1N2 0.1 UF 10% 25 V X7R 603 DB9A1 1 PSU_V12P0_EN_R 1 2 C9A2 1 0.1 UF 10% 6.3 V 2 X5R 402 C9A1 470 PF 5% 50 V EMPTY 402 11 12 J9A1 CONN 12P_PWR_RCPT GND GND GND GND +12V MAIN +12V MAIN +12V MAIN +12V MAIN POWER ENABLE +5V STANDBY MH1 MH2 X863226-003 TH B C9B2 470 PF 5% 50 V X7R 402 A A MICROSOFT DRAWING Tue Jun 18 16:42:28 2013 CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 41/72 2 CSA PAGE 41/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 VREGS, BLEEDERS D D V_5P0STBY C V_12P0 1 R2N7 1 1 BLEEDER_V12P0_C1 BLEEDER_V12P0_C2 1 2 549 OHM 1% CH 402 DB8C2 26 29 1 1 PSU_V12P0_EN IN 1 2 2.2 KOHM 5% CH 402 DB8C1 BLEEDER_V12P0_B1 1 U8B3 XSTR 24 BLEEDER_V12P0_LOAD R2N11 1 R2N12 10 OHMS 10 OHMS 1% 1% 2 CH 2 CH 1206 1206 1 U2N3 FET 2 SOT23 1 R2N13 1 R2N10 10 OHMS 10 OHMS 1% 1% 2 CH 2 CH 1206 1206 1 R4B3 20 OHM 5% 2 CH 1206 1 R4B4 20 OHM 5% 2 CH 1206 1 R4B2 20 OHM 5% 2 CH 1206 1 R4B5 20 OHM 5% 2 CH 1206 3 1 U2N4 65 29 XSTR 2 R8C1 V12P0_PWRGD IN 3 R8C2 1 BLEEDER_V12P0_B2 R4B6 10 KOHM 5% 2 CH 402 3 R2N8 3 DB4B1 V_12P0 2.2 KOHM 5% 2 CH 402 BLEEDER_C2 R2N9 2.2 KOHM 5% 2 CH 402 BLEEDER_C1 1 B C V_5P0DUAL IN SMC_RST_N 3 R4B1 1 2 10 KOHM 5% CH 402 BLEEDER_B 1 U4B1 XSTR 2 B U4B2 XSTR 2 1 2 2.2 KOHM 5% CH 402 1 V_5P0DUAL BLEEDER V_12P0 BLEEDER A A MICROSOFT [PAGE_TITLE=VREGS, INPUT + OUTPUT FILTERS] 8 7 6 DRAWING Tue Jun 18 16:42:20 2013 CONFIDENTIAL 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 42/72 2 CSA PAGE 42/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 VREGS, INPUT + OUTPUT FILTERS D D IO/NBCORE/MEMCORE INPUT FILTER V_12P0 V_12P0 L9B2 1 2 0.68 UH 15.5 A 0.005 OHM V_VREG_12P0_MEM_NBCORE IND SM 1 C9B7 C 2 470 UF 20% 16 V POLY TH OUT 50 51 52 53 1 C9B14 1 2 2 10 UF 10% 16 V X5R 805 0.68 UH 15.5 A 0.005 OHM C8B11 10 UF 10% 16 V X5R 805 V_GFXCORE OUTPUT FILTER V_GFXCORE 1 1 C8E1 B 2 1 C8D4 820 UF 20% 2.5 V POLY RDL GFX/CPU INPUT FILTER L9B1 1 2 2 820 UF 20% 2.5 V POLY RDL 1 C8D2 2 820 UF 20% 2.5 V POLY RDL V_VREG_12P0_GFXCPU 1 C9B12 2 1 C9B8 470 UF 20% 16 V POLY TH 2 V_CPUCORE 1 C9B4 470 UF 20% 16 V POLY TH 2 1 470 UF 20% 16 V POLY TH 2 C9B9 1 10 UF 10% 16 V X5R 805 2 C9B10 10 UF 10% 16 V X5R 805 1 1 C8E5 820 UF 20% 2.5 V POLY RDL 2 C V_CPUCORE OUTPUT FILTER FTP FT2R1 1 C8D1 2 44 46 47 48 OUT IND SM 820 UF 20% 2.5 V POLY RDL 1 C8E8 2 820 UF 20% 2.5 V POLY RDL FTP FT1T1 C8E10 820 UF 20% 2.5 V 2 POLY RDL 1 B 5P0/3P3 INPUT FILTER V_12P0 L8B1 1 2 0.68 UH 15.5 A 0.005 OHM V_VREG_12P0_TO_5P0_3P3 IND SM 1 C8B18 A 2 470 UF 20% 16 V POLY TH OUT 30 54 56 1 C8B17 2 4.7 UF 10% 16 V X5R 1206 A MICROSOFT [PAGE_TITLE=VREGS, INPUT + OUTPUT FILTERS] 8 7 6 DRAWING Tue Jun 18 16:42:25 2013 CONFIDENTIAL 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 43/72 2 CSA PAGE 43/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 VREGS, CPUCORE V_5P0 8 SOC_CPUCORE_S IN D D 26 VREG_GFXCPU_RAMP VCC 12 VRMP FT1P7 FTP 52 1 IN C R9C1 SMBUS_CLK 1 2 0 OHM 5% 402 CH SMBUS_DATA R9C2 1 2 36.5 OHM1% CH 402 1 1 DB9C7 DB9C8 IN VREG_CPUCORE_FB VREG_CPUCORE_COMP VREG_CPUCORE_TRBST SMBUS_DATA_CPUCORE R1P19 1 2.8 KOHM 1% CH 2 R9C39 402 1 2 VREG_CPUCORE_CSCOMP_R FT1P1 FTP 8 BI 18.2 OHM1% 402 CH FT1P3 FTP IN SVC R2R3 1 2 1 18.2 OHM 1% CH 402 FT1P2 FTP 8 OUT 1 603 THRMSTR X863133-001 48 165 KOHM 1% CH 2 402 IN 1 1 KOHM 1% CH 402 26 21 20 CSN1 22 24 CSCOMP CSSUM 2 8 C9C18 1500 PF 10% 50 V X7R 402 10 KOHM 5% 2 CH 2 27 1 2 VREG_CPUCORE_COMP_R 1 OCP_L DRON IOUT 43.2 KOHM1% CH 402 1 2 C9C13 470 PF 5% 50 V X7R 402 QFN53 7 FREQUENCY = 400KHZ, CHANGED OVER I2C SEE DATASHEET FOR REGISTER TABLE 46 47 48 R9C55 1 10 KOHM 1% CH 2 402 SLEW RATE SET BY SR RES ON PIN 27 SLEW RATE RESISTANCE NCP4204 I2C ADDRESS 0000 000 R/W HEX WRITE 0100 000 0 0X40 READ 0100 000 1 0X41 SVC 0 0 1 1 0 OHM 5% 402 EMPTY R9C38 1 2 10 KOHM 1% CH 402 6 OUT OUT R9C45 28.7 KOHM 1% CH 402 SVD 0 1 0 1 10MV/US 20MV/US 30MV/US 10 KOHM 25 KOHM 45 KOHM BOOT VOLTAGE 1.1V 1.0V 0.9V 0.8V MICROSOFT CONFIDENTIAL 8 DB1P2 13 VREG_OCP_L 32 VREG_GFXCPU_DRV_EN 23 VREG_CPUCORE_IOUT AGND B 48 A R9C35 2 2VREG_VDD_TRBST_C1 470 PF 5% 50 V EMPTY R9C29 1 2 VREG_CPUCORE_TRBST_R 402 OUT 1 68 PF 5% 50 V NPO 402 5.9 KOHM 1% CH 402 C9C15 1500 PF 10% 50 V X7R 402 VREG_CPUCORE_PWM C1P9 1500 PF 10% 50 V X7R 402 TO INCREASE CURRENT LIMIT INCREASE ILIM RES ON PIN 20 RES OF 30KOHM EFFECTIVELY REMOVES CURRENT LIMIT R9C36 SOC_GFXCPU_S_RTN IN 1 R9C17 PWM1/SR 1 C9C16 C9C11 C V_SOC1P8 X861898-002 VREG_CPUCORE_FB 1 DROOP ILIM 18.2 OHM1% CH 402 150 OHMS1%VREG_CPUCORE_FB_C 1500 PF 10% CH 402 50 V X7R 402 R9C23 1 2 FB COMP TRBST VREG_CPUCORE_CSSUM 44 C9C12 16 19 18 53 DB9C1 IN 48 DB2P1 RT9E1 1 2 R9C21 2 VREG_CPUCORE_DIFFOUT IN 44 402 1 1 A 73.2 KOHM1% CH 402 R9C43 1 1 2 10 OHM 1% 402 CH 1 SVT R9C32 R9C4 SVD_R VREG_CPUCORE_CSN_R VREG_CPUCORE_DROOP VREG_CPUCORE_ILIM 1 R9C40 C9C20 2200 PF 28.7 KOHM 10% 1% 50 V 2 CH X7R 402 402 VREG_CPUCORE_CSCOMP VREG_CPUCORE_CSN1 2 10 OHM 1% CH 402 IN SVD VREG_CPUCORE_CSP 1 SMBUS_CLK_CPUCORE B 8 25 SVD SVC SVT BI R2R2 1 2 CSP1 1 3 2 R9C54 BI OUT SCL SDA 48 66 65 64 50 40 26 54 53 52 VREG_CPUCORE_S VREG_CPUCORE_DIFFOUT VREG_GFXCPU_S_RTN 5 6 DB9C3 OUT PWROK 15 17 14 1 SVD_R_CPUCORE SVC_R SVT_R 1 2 0 OHM 5% 805 EMPTY VENABLE VDD DIFF VSS EN 10 KOHM 5% 2 CH 402 52 50 40 65 26 66 64 54 53 VDDIO 9 FT1P4 FTP 7 R2R1 VREG_CPUCORE_EN 1 R1P10 VDD_PWRGD 2 11 4 SOC_PWR_OK IN IC NCP4204 SHORT 2 C9C9 2.2 UF 10% 6.3 V X5R 603 U9C2 SHORT 1 0 OHM 5% 2 EMPTY 402 ST1T1 2 2 1 R1P9 C9C8 1 UF 10% 16 V X5R 603 OUT FTP FT1P5 1 1 1 45 26 69 2 1 KOHM 1% CH 402 VREG_CPUGFX_PWRGD ST2R1 V_VREG_12P0_GFXCPU IN C1P7 1 UF 10% 16 V X5R 603 1 43 V_SOC1P8 1 R1P8 1 2 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 44/72 2 CSA PAGE 44/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 VREGS, GFXCORE 8 SOC_GFXCORE_S IN D D VREG_CPUGFX_PWRGD 2 R2P5 VREG_GFXCORE_EN IN FT1P6 FTP 10 VDDNB_PWRGD EN_NB 1 1 2 0 OHM 5% 805 EMPTY 8 VDDNB DIFFNB 51 50 VREG_GFXCORE_S VREG_GFXCORE_DIFFOUT CSP1NB CSP2NB CSP3NB CSP4NB 33 37 35 40 VREG_GFXCORE_CSP1 VREG_GFXCORE_CSP2 VREG_GFXCORE_CSP3 VREG_GFXCORE_CSP4 OUT 45 IN IN IN IN 46 46 47 47 OUT 45 SHORT DB1P3 NCP4204 ST2R2 1 IC OUT 1 U9C2 44 26 69 VENABLE 1 R9C18 1 10 KOHM 5% DB9C2 2 CH 402 VREG_GFXCORE_DIFFOUT C IN R9C24 1 2 1 DB9C4 45 C1P3 DB9C5 2 1 C9C14 VREG_GFXCORE_FB VREG_GFXCORE_COMP VREG_GFXCORE_TRBST 1 1 C1P4 2 VREG_GFXCORE_CSCOMP_R R1P18 1 2 47 46 IN 2 C1P6 2 VREG_GFXCORE_TRBST_C 470 PF 5% 50 V EMPTY 402 2 VREG_GFXCORE_TRBST_R 43.2 KOHM 1% 402 CH R9C44 1 1 470 PF 5% 50 V X7R 402 CSN1NB VREG_GFXCORE_CSREF VREG_GFXCORE_DROOP VREG_GFXCORE_ILIM R1P17 1 2 10 KOHM 1% CH 402 44.2 KOHM 1% CH 402 IN CSN3NB 36 CSN4NB 39 41 45 46 CSREFNB DROOPNB ILMNB R9C41 2.1 KOHM 1% 2 CH 402 1 C9C17 44 43 CSCOMPNB CSSUMNB C1P10 2200 PF 10% 50 V X7R 402 2 TO INCREASE CURRENT LIMIT INCREASE ILIM RES ON PIN 20 RES OF 30KOHM EFFECTIVELY REMOVES CURRENT LIMIT PWM2NB/ICCMAX PWM3NB/ICCMAXNB PWM4NB 2200 PF 10% 50 V X7R 402 1 C9C19 1500 PF 10% 50 V X7R 402 VREG_GFXCORE_CSREF R1P24 1 2 10 OHM 1% CH 402 1 R1P21 10 OHM 1% 2 402 CH 1 R1P25 2 10 OHM 1% CH 402 2 1 C1P15 0.01 UF 10% 16 V X7R 402 VREG_GFXCORE_CSN1 VREG_GFXCORE_CSN2 VREG_GFXCORE_CSN3 VREG_GFXCORE_CSN4 PWM1NB/SRNB 73.2 KOHM1% CH 402 603 THRMSTR X863133-001 38 R1P20 2 1 10 OHM 1% CH 402 R9C30 VREG_GFXCORE_CSCOMP 34 CSN2NB R9C33 1 2 200 OHM 1% 402 EMPTY 45 C FBNB COMPNB TRBSTNB 7.32 KOHM 1% 402 CH 1000 PF 10% 50 V X7R 402 1 RT9D1 1 2 48 47 49 100 PF 5% 50 V NPO 402 R9C37 2 VREG_GFXCORE_COMP_R R9C28 165 KOHM 1% CH 2 402 DB9C6 1 C1P8 R9C26 1 2 B 1 VREG_GFXCORE_FB VREG_GFXCORE_FB_C 49.9 OHM 1% 2200 PF 10% CH 402 50 V X7R 402 1 KOHM 1% CH 402 1 IOUTNB 31 29 30 28 QFN53 46 46 47 47 B VREG_GFXCORE_PWM1 VREG_GFXCORE_PWM2 VREG_GFXCORE_PWM3 VREG_GFXCORE_PWM4 OUT OUT OUT OUT 46 46 47 47 R1R6 1 10 KOHM 1% CH 2 402 42 VREG_GFXCORE_IOUT R9C48 X861898-002 IN IN IN IN 23.7 KOHM 1% CH 402 R1R9 1 30.1 KOHM 1% CH 2 402 VREG_GFXCORE_CSSUM R1R12 1 130 KOHM 1% CH 2 402 R1T3 1 10 KOHM 1% CH 2 402 A PWM4NB RES ON PIN 28 SETS I2C ADDRESS SEE DATASHEET FOR ADDRESS TABLE A SLEW RATE SET BY SRNB RES ON PIN 31 SLEW RATE RESISTANCE 10MV/US 20MV/US 30MV/US MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 45/72 2 10 KOHM 25 KOHM 45 KOHM CSA PAGE 45/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 VREGS, GFXCORE OUTPUT PHASE 1 & 2 V_VREG_12P0_GFXCPU V_5P0 1 Q9D1 NTTFS4928N X862002-001 DFN5 FET 1 R1R4 45 44 IN IN 4 0.1 UF 10% 25 V X7R 603 2 1 OHM 1% CH 805 2 VREG_GFXCORE_DRVL1 Q9D2 NTMFS4985NF X866717-001 DFN5 FET 4 1 2 3 1 IND SM VREG_GFXCORE_CSN1 1000 PF 10% 50 V X7R 603 OUT 45 OUT 45 OUT 46 47 45 1 C9C24 1 R1P26 1 KOHM 5% 1 C9D1 2 230 NH 61 A 0.00029 OHM SHORT 1 R9D2 X863210-001 DFN9 R1R5 2VREG_GFXCORE_PH1_EN NOM.VOLTAGE: 0.9-1.1V L9D1 1 2 VREG_GFXCORE_SW1 1 V_GFXCORE V_GFXCORE VREG_GFXCORE_DRVH1 49.9 OHM 1% CH 402 C 2 ST9D1 1 8 7 5 2 2 BST DRVH SW DRVL C9D5 2 1 UF 10% 16 V X7R 805 VCC PWM EN GND MPAD 2.2 OHM1% 805 CH 1 D 1 C1R2 10 UF 10% V 2 16 EMPTY 805 SHORT 1 C9D4 2 VREG_GFXCORE_PWM1 VREG_GFXCPU_DRV_EN 4 2 3 6 9 VREG_GFXCORE_BST1_R ST9D2 VREG_GFXCORE1_VCC IC R9D5 2 10 UF 10% 16 V X5R 805 VREG_GFXCORE_SW1_R 2.2 OHM 1% CH 402 U9D2 NCP5901B 1 1 C1R1 10 UF 10% V 2 16 EMPTY 805 C9D3 1 2 3 1 VREG_GFXCORE_BST1 5 R9D4 2 2.2 OHM 1% 2 EMPTY 402 1 C9D2 10 UF 10% 16 V X5R 805 1 D VREG_GFXCORE_SW1_S IN 5 43 0.15 UF 10% V 2 16 X7R 402 603 VREG_GFXCORE_CSP1 2 EMPTY R9C59 2 1 5.9 KOHM 1% CH 603 R1P29 VREG_GFXCORE_CSSUM 20 KOHM 1% CH 402 C V_5P0 1 R1R7 B B VREG_GFXCORE2_VCC 1 1 C9D9 1 8 7 5 1 2 3 VREG_GFXCORE_SW2 X863210-001 DFN9 I69 I70 I71 ZZ400 I75 I72 I73 I74 ZZ401 I76 FET FET FET FET FET FET FET FET TRA-N-CNL,SM,WDFN8,8.9 MOHM,30 V,24 A TRA-N-CNL,SM,WDFN8,10 MOHM,30 V,27 A TRA-N-CNL,SM,WDFN8,9 MOHM,30 V,12 A TRA-N-CNL,SM,WDFN8,8.8 MOHM,30 V,24 A TRA-N-CNL,SM,SO-8FL,3.1 MOHM,30 V,50 A TRA-N-CNL,SM,SO-8FL,3.5 MOHM,30 V,35 A TRA-N-CNL,SM,SO-8FL,4.5 MOHM,30 V,24 A TRA-N-CNL,SM,SO-8FL,3.6 MOHM,30 V,32 A TRUEDESCR. BOM PROPERTY FET_CPUGFX_IRF TRUE FET_CPUGFX_TOS TRUE FET_CPUGFX_STM TRUE FET_CPUGFX_AOS TRUE FET_CPUGFX_IRF TRUE FET_CPUGFX_TOS TRUE FET_CPUGFX_STM TRUE FET_CPUGFX_AOS 1 2 3 A MATL REF_DES X875319-001 X875313-001 X876425-001 X875316-001 X875320-001 X875312-001 X878211-001 X875317-001 Q9D4 NTMFS4985NF X866717-001 DFN5 FET 4 230 NH IND 61 A SM 0.00029 OHM 1 R9D6 1 OHM 1% CH 805 2 VREG_GFXCORE_DRVL2 MS_PART# Q9D1,Q9D3 Q9D1,Q9D3 Q9D1,Q9D3 Q9D1,Q9D3 Q9D2,Q9D4 Q9D2,Q9D4 Q9D2,Q9D4 Q9D2,Q9D4 L9D2 1 2 VREG_GFXCORE_DRVH2 1 BST DRVH SW DRVL SHORT VCC PWM EN GND MPAD V_GFXCORE ST9D3 49.9 OHM1% CH 402 4 2 3 6 9 2 2 R1R8 2 VREG_GFXCORE_PH2_EN 1 4 0.1 UF 10% 25 V X7R 603 2 1 VREG_GFXCORE_PWM2 VREG_GFXCORE_BST2_R 2.2 OHM1% 805 CH 2 Q9D3 NTTFS4928N X862002-001 DFN5 FET SHORT IN IC 1 C9D10 1 C1R4 10 UF 10% V 2 16 EMPTY 805 1 C1R3 10 UF 10% V 2 16 EMPTY 805 C9D7 10 UF 10% 16 V X5R 805 ST9D4 45 VREG_GFXCORE_BST2 U9D3 NCP5901B R9D8 1 2 1 5 2 1 UF 10% 16 V X7R 805 C9D8 10 UF 10% 16 V X5R 805 VREG_GFXCORE_SW2_R 2.2 OHM 1% CH 402 VREG_GFXCORE_CSN2 1 KOHM 5% 2 EMPTY 402 R9C57 1 2 VREG_GFXCORE_SW2_S 1 C9D6 1000 PF 10% OUT 2 0.15 UF 10% 16 V X7R 603 VREG_GFXCORE_CSP2 R9C58 603 VREG_GFXCORE_CSSUM 20 KOHM 1% CH 402 MICROSOFT 8 7 6 5 4 3 A OUT 45 OUT 46 47 45 5.9 KOHM 1% CH 603 V 2 50 X7R DRAWING Tue Jun 18 16:42:25 2013 CONFIDENTIAL 45 1 C9C26 1 R1P28 2 R9D7 2 1 5 2.2 OHM 1% 2 EMPTY 402 PROJECT NAME PAGE GREYBULL_RETAIL 46/72 2 CSA PAGE 46/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 VREGS, GFXCORE OUTPUT PHASE 3 & 4 V_VREG_12P0_GFXCPU V_5P0 1 Q9D5 NTTFS4928N X862002-001 DFN5 FET 1 R1R10 44 C IN VREG_GFXCPU_DRV_EN Q9D6 NTMFS4985NF X866717-001 DFN5 FET 4 1 49.9 OHM 1% CH 402 1 C9D11 1000 PF 10% 50 V X7R 603 2 1 1 OHM 1% CH 805 2 ST9D5 X863210-001 DFN9 230 NH IND 61 A SM 0.00029 OHM 1 R9D9 SHORT VREG_GFXCORE_SW3 VREG_GFXCORE_DRVL3 NOM.VOLTAGE: 0.9-1.1V V_GFXCORE L9D3 1 2 VREG_GFXCORE_DRVH3 R1R11 2VREG_GFXCORE_PH3_EN V_GFXCORE 2 IN VREG_GFXCORE_PWM3 1 8 7 5 1 2 3 45 BST DRVH SW DRVL 0.1 UF 10% 25 V X7R 603 D 2 2 1 UF 10% 16 V X7R 805 VCC PWM EN GND MPAD 4 2 1 C1R6 10 UF 10% V 2 16 EMPTY 805 SHORT 1 C9D14 4 2 3 6 9 2.2 OHM1% 805 CH C9D15 ST9D6 VREG_GFXCORE3_VCC VREG_GFXCORE_BST3_R1 2 1 C1R5 10 UF 10% V 2 16 EMPTY 805 VREG_GFXCORE_SW3_R 2.2 OHM 1% CH 402 IC U9D4 NCP5901B R9D11 1 2 5 R9D10 1 2 VREG_GFXCORE_BST3 2 C9D12 10 UF 10% 16 V X5R 805 1 2 3 2.2 OHM 1% 2 EMPTY 402 1 C9D13 10 UF 10% 16 V X5R 805 VREG_GFXCORE_CSN3 1 D VREG_GFXCORE_SW3_S IN 5 43 1 R1P27 2 0.15 UF 10% 16 V X7R 603 VREG_GFXCORE_CSP3 5.9 KOHM 1% CH 603 R1P30 C 1 C9C25 1 KOHM 5% 2 EMPTY 402 R9C60 1 2 45 OUT VREG_GFXCORE_CSSUM 20 KOHM 1% CH 402 OUT 45 OUT 46 47 45 V_5P0 B 1 R9E2 B VREG_GFXCORE4_VCC 1 1 C9E4 1 8 7 5 VREG_GFXCORE_SW4 1 R9E1 X863210-001 DFN9 Q9E2 NTMFS4985NF X866717-001 DFN5 FET 4 1 2 3 A I73 I74 I72 ZZ402 I76 I71 I70 I69 ZZ403 I75 MATL REF_DES X875319-001 X875313-001 X876425-001 X875316-001 X875320-001 X875312-001 X878211-001 X875317-001 FET FET FET FET FET FET FET FET TRA-N-CNL,SM,WDFN8,8.9 MOHM,30 V,24 A TRA-N-CNL,SM,WDFN8,10 MOHM,30 V,27 A TRA-N-CNL,SM,WDFN8,9 MOHM,30 V,12 A TRA-N-CNL,SM,WDFN8,8.8 MOHM,30 V,24 A TRA-N-CNL,SM,SO-8FL,3.1 MOHM,30 V,50 A TRA-N-CNL,SM,SO-8FL,3.5 MOHM,30 V,35 A TRA-N-CNL,SM,SO-8FL,4.5 MOHM,30 V,24 A TRA-N-CNL,SM,SO-8FL,3.6 MOHM,30 V,32 A 1 OHM 1% CH 805 2 VREG_GFXCORE_DRVL4 MS_PART# Q9D5,Q9E1 Q9D5,Q9E1 Q9D5,Q9E1 Q9D5,Q9E1 Q9D6,Q9E2 Q9D6,Q9E2 Q9D6,Q9E2 Q9D6,Q9E2 L9E1 1 2 VREG_GFXCORE_DRVH4 2 VREG_GFXCORE_SW4_S 1000 PF 10% 50 V X7R 603 6 2 0.15 UF 10% 16 V X7R 603 R9C52 1 2 VREG_GFXCORE_CSP4 R9C56 VREG_GFXCORE_CSSUM 20 KOHM 1% CH 402 5 4 3 45 A 45 OUT 5.9 KOHM 1% CH 603 MICROSOFT 7 OUT 1 C9C21 1 KOHM 5% 2 EMPTY 402 DRAWING Tue Jun 18 16:42:25 2013 CONFIDENTIAL 8 VREG_GFXCORE_CSN4 1 R9C51 1 C9E1 TRUEDESCR. BOM PROPERTY FET_CPUGFX_IRF TRUE FET_CPUGFX_TOS TRUE FET_CPUGFX_STM TRUE FET_CPUGFX_AOS TRUE FET_CPUGFX_IRF TRUE FET_CPUGFX_TOS TRUE FET_CPUGFX_STM TRUE FET_CPUGFX_AOS 230 NH IND 61 A SM 0.00029 OHM SHORT BST DRVH SW DRVL 1 VCC PWM EN GND MPAD ST9E1 49.9 OHM1% CH 402 4 2 3 6 9 V_GFXCORE 2 2 VREG_GFXCORE_PH4_EN 0.1 UF 10% 25 V X7R 603 2 SHORT R1T2 4 2 1 1 2.2 OHM 1% 805 CH 2 Q9E1 NTTFS4928N X862002-001 DFN5 FET ST9E2 VREG_GFXCORE_PWM4 IN IC U9E1 NCP5901B VREG_GFXCORE_BST4_R 1 C9E5 1 C1T2 10 UF 10% V 2 16 EMPTY 805 VREG_GFXCORE_SW4_R 45 VREG_GFXCORE_BST4 R9E3 1 2 1 C1T1 10 UF 10% V 2 16 EMPTY 805 C9E3 10 UF 10% 16 V X5R 805 1 2 3 2 1 UF 10% 16 V X7R 805 1 C9E2 10 UF 10% 16 V X5R 805 5 2.2 OHM 1% CH 402 2 R1T1 2 1 5 2.2 OHM 1% 2 EMPTY 402 PROJECT NAME PAGE GREYBULL_RETAIL 47/72 2 OUT CSA PAGE 47/72 1 46 47 45 FAB REV M 1.0 8 7 6 5 4 3 2 1 VREGS, CPUCORE OUTPUT PHASE D D Q9E3 NTTFS4928N X862002-001 DFN5 FET 1 R1T4 L9E2 VREG_CPUCORE_SW 1 OHM 1% CH 805 1 C9E6 2 1000 PF 10% 50 V X7R 603 C SHORT 4 VREG_CPUCORE_PH_EN 2 1 Q9E4 NTMFS4985NF X866717-001 DFN5 FET 2 1 R9E4 49.9 OHM 1% CH 402 2 300 NH IND 42 A SM 0.00047 OHM X863210-001 DFN9 VREG_CPUCORE_DRVL 1 ST9E3 R1T5 2 1 NOM.VOLTAGE: 0.8-1.2V V_CPUCORE VREG_CPUCORE_DRVH VREG_CPUCORE_PWM VREG_GFXCPU_DRV_EN V_CPUCORE 2 1 8 7 5 0.1 UF 10% 25 V X7R 603 1 C1T4 10 UF 10% V 2 16 EMPTY 805 SHORT IN BST DRVH SW DRVL 4 2 1 2 3 IN 1 UF 10% 16 V X7R 805 VCC PWM EN GND MPAD 2.2 OHM1% 805 CH C9E10 ST9E4 2 44 4 2 3 6 9 1 C9E9 IC 1 1 C1T3 10 UF 10% V 2 16 EMPTY 805 1 VREG_CPUCORE_VCC C 44 U9E2 NCP5901B R9E6 1 2 VREG_CPUCORE_BST_R 2 C9E7 10 UF 10% 16 V X5R 805 5 2.2 OHM 1% CH 402 VREG_CPUCORE_BST 2 1 C9E8 10 UF 10% 16 V X5R 805 1 2 3 2.2 OHM 1% 2 EMPTY 402 R9E5 1 2 1 5 V_5P0 VREG_CPUCORE_CSN VREG_CPUCORE_SW_S IN V_VREG_12P0_GFXCPU VREG_CPUCORE_SW_R 43 OUT 44 VREG_CPUCORE_CSP OUT 44 VREG_CPUCORE_CSSUM OUT 44 1 C9C23 1 R9C53 1 KOHM 5% 2 EMPTY 402 R9C50 1 2 2 0.15 UF 10% 16 V X7R 603 7.15 KOHM1% CH 402 R9C49 1 2 19.6 KOHM 1% 402 CH B I39 I38 I37 ZZ410 I43 I36 I41 I40 ZZ411 I42 MS_PART# Q9E3 Q9E3 Q9E3 Q9E3 Q9E4 Q9E4 Q9E4 Q9E4 MATL REF_DES X875319-001 X875313-001 X876425-001 X875316-001 X875320-001 X875312-001 X878211-001 X875317-001 FET FET FET FET FET FET FET FET TRA-N-CNL,SM,WDFN8,8.9 MOHM,30 V,24 A TRA-N-CNL,SM,WDFN8,10 MOHM,30 V,27 A TRA-N-CNL,SM,WDFN8,9 MOHM,30 V,12 A TRA-N-CNL,SM,WDFN8,8.8 MOHM,30 V,24 A TRA-N-CNL,SM,SO-8FL,3.1 MOHM,30 V,50 A TRA-N-CNL,SM,SO-8FL,3.5 MOHM,30 V,35 A TRA-N-CNL,SM,SO-8FL,4.5 MOHM,30 V,24 A TRA-N-CNL,SM,SO-8FL,3.6 MOHM,30 V,32 A TRUEDESCR. BOM PROPERTY FET_CPUGFX_IRF TRUE FET_CPUGFX_TOS TRUE FET_CPUGFX_STM TRUE FET_CPUGFX_AOS TRUE FET_CPUGFX_IRF TRUE FET_CPUGFX_TOS TRUE FET_CPUGFX_STM TRUE FET_CPUGFX_AOS B A A MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 48/72 2 CSA PAGE 48/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 VREGS, VTT TERMINATION V_5P0 V_3P3 D 10 KOHM 5% 2 CH 402 C8C7 U8C2 IC TPS51206 1 UF 10% 6.3 V X5R 402 2 2 VLDOIN V_VTTD VDD 10 VTT 3 1 7 9 VREG_VTTA_EN V_MEMIOCD 1 VREG_VTTA_SNS V_MEMIOCD R8C15 1 0 OHM 5% 2 CH 402 R8C13 VDDQSNS VTTSNS 5 VREG_VTTA_VO VTTREF 6 VREG_VTTA_REFOUT 4 8 11 PGND GND MPAD S3 S5 1 X864012-001 SON11 2 C8C5 1 UF 10% 6.3 V X5R 402 ST9C1 2 1 UF 10% 6.3 V X5R 402 2 1 C9C3 10 UF 20% 6.3 V X5R 805 2 1 C9C1 10 UF 20% 6.3 V X5R 805 2 FT1P9 FTP C9C7 2 V_VTTC VDD 10 VTT 3 1 2 VLDOIN 1 C9C4 1 2 V_MEMIOCD 1 2 1 1 10 UF 20% 6.3 V X5R 805 R4R5 VTTSNS 5 VREG_VTTB_VO VTTREF 6 VREG_VTTB_REFOUT PGND GND MPAD S3 S5 4 8 11 1 X864012-001 SON11 2 DB6D5 1 2 1 2 0 OHM 5% SHORT CH 402 1 C4R12 1 UF 10% 6.3 V X5R 402 FTP FT4R3 1 ST4R1 2 C4R13 C4R22 1 1 1 UF 10% 6.3 V X5R 402 2 1 C4R20 10 UF 20% 6.3 V X5R 805 2 C4R31 1 10 UF 20% 6.3 V X5R 805 C4R26 1 10 UF 20% 6.3 V X5R 805 2 FT4R2 FTP 1 2 2 C4R28 C 2 1 UF 10% 6.3 V X5R 402 C4R32 1 2 1 DB6D4 C4R15 1 UF 10% 6.3 V X5R 402 1 1 2 1 UF 10% 6.3 V X5R 402 R4R3 1 KOHM 1% 2 EMPTY 402 1 UF 10% 6.3 V X5R 402 C8C6 R4R1 0 OHM 5% 2 CH 402 R4R2 1 KOHM 1% 2 EMPTY 402 1 UF 10% 6.3 V X5R 402 C9C2 1 2 1 7 9 VREG_VTTB_EN 1 UF 10% 6.3 V X5R 402 C9C6 VDDQSNS 2 V_MEMIOCD 22 UF 20% 6.3 V X7R 805 R8C14 1 C9C10 1 UF 10% 6.3 V X5R 402 1 DB9C9 1 KOHM 1% 2 EMPTY 402 1 UF 10% 6.3 V X5R 402 DB9C10 1 1 KOHM 1% 2 EMPTY 402 1 2 U4R1 IC TPS51206 C4R9 1 1 C9C5 10 KOHM 5% 2 CH 402 FTP FT1P8 1 1 2 1 2 0 OHM 5% SHORT CH 402 1 1 1 R4R4 1 R9C3 D VREG_VTTB_SNS 1 1 R8C9 C POWERED BY V3P3 DUE TO PHYSICAL LAYOUT CONSTRAINTS EXHIBITS CORRECT FUNCTIONALITY 1 UF 10% 6.3 V X5R 402 C4R6 10 UF 20% 6.3 V X5R 805 V_5P0 V_5P0 B B 2 U9F4 IC TPS51206 C9F11 1 UF 10% 6.3 V X5R 402 VDD VREG_VTTC_EN V_MEMIOAB V_MEMIOAB 1 1 R9F15 1 KOHM 1% 2 EMPTY 402 A 1 2 VLDOIN 1 VDDQSNS 7 9 S3 S5 V_VTTB 1 VTT 3 VTTSNS 5 VTTREF 6 PGND GND MPAD X864012-001 SON11 1 R6E29 10 1 ST9F1 1 2 1 2 0 OHM 5% SHORT CH 402 VREG_VTTC_REFOUT 4 8 11 1 2 C9F12 1 UF 10% 6.3 V X5R 402 1 2 C9F13 1 UF 10% 6.3 V X5R 402 2 1 C9F20 10 UF 20% 6.3 V X5R 805 2 1 C9F19 10 UF 20% 6.3 V X5R 805 2 C9F16 10 UF 20% 6.3 V X5R 805 R9F14 0 OHM 5% 2 CH 402 DB9F6 2 1 C9F17 C8F7 2 2 1 UF 10% 6.3 V X5R 402 C9F18 1 2 1 1 1 UF 10% 6.3 V X5R 402 C9F10 10 UF 20% 6.3 V X5R 805 V_MEMIOAB V_MEMIOAB 1 R6E32 1 R6E31 0 OHM 5% 2 CH 402 10 VLDOIN VTT 3 VDDQSNS 7 9 S3 S5 VTTSNS 5 VTTREF 6 PGND GND MPAD X864012-001 SON11 R6E19 VREG_VTTD_VO VREG_VTTD_REFOUT 4 8 11 1 UF 10% 6.3 V X5R 402 1 2 C6E13 1 C6E12 1 UF 10% 6.3 V X5R 402 2 2 C6E5 10 UF 20% 6.3 V X5R 805 1 2 1 C6E8 10 UF 20% 6.3 V X5R 805 2 C6E10 1 10 UF 20% 6.3 V X5R 805 FT4T4 FTP DB6E2 1 4 C6E4 2 1 UF 10% 6.3 V X5R 402 C6E9 2 1 UF 10% 6.3 V X5R 402 C6E7 1 2 1 1 R6E30 1 KOHM 1% 2 EMPTY 402 [PAGE_TITLE=VTT TERMINATION] 5 1 1 UF 10% 6.3 V X5R 402 1 UF 10% 6.3 V X5R 402 C6E17 10 UF 20% 6.3 V X5R 805 MICROSOFT CONFIDENTIAL 6 DB6E1 C6E11 1 2 1 2 1 2 0 OHM 5% SHORT CH 402 1 KOHM 1% 2 EMPTY 402 1 FTP FT4T3 1 ST6E2 1 2 7 V_VTTA VDD 1 2 VREG_VTTD_EN NOTE: VOSNS SHOULD BE CONNECTED AS A SEPARATE TRACE FROM VO PATH 8 U6E4 IC TPS51206 1 UF 10% 6.3 V X5R 402 1 1 UF 10% 6.3 V X5R 402 1 FT7P11 FTP 1 DB9F5 C9F14 1 2 2 C6E16 1 UF 10% 6.3 V X5R 402 1 R9F16 1 KOHM 1% 2 EMPTY 402 1 R9F18 VREG_VTTC_VO FTP FT1U6 10 KOHM 5% 2 CH 402 VREG_VTTD_SNS 1 10 KOHM 5% 2 CH 402 VREG_VTTC_SNS 1 R9F17 DRAWING Tue Jun 18 16:42:25 2013 3 PROJECT NAME PAGE GREYBULL_RETAIL 49/72 2 CSA PAGE 49/72 1 FAB REV M 1.0 A 8 7 6 5 4 3 2 1 VREGS, NBCORE D 43 IN V_VREG_12P0_MEM_NBCORE I295 I296 1 C5F7 R5F13 2 2 1 2.2 OHM 1% CH 402 1 C5F8 2 1 C5U4 10 UF 10% 16 V X5R 805 2 1 C5U3 10 UF 10% 16 V EMPTY 805 2 I294 10 UF 10% 16 V EMPTY 805 ZZ412 I301 I291 I293 I292 ZZ413 I300 1 C5F4 1 UF 10% V 2 16 X7R 805 MS_PART# Q5F1 Q5F1 Q5F1 Q5F1 Q5F2 Q5F2 Q5F2 Q5F2 MATL REF_DES X875319-001 X875313-001 X876425-001 X875316-001 X875320-001 X875312-001 X878211-001 X875317-001 FET FET FET FET FET FET FET FET TRUEDESCR. BOM PROPERTY FET_MEMNB_IRF TRUE FET_MEMNB_TOS TRUE FET_MEMNB_STM TRUE FET_MEMNB_AOS TRUE FET_MEMNB_IRF TRUE FET_MEMNB_TOS TRUE FET_MEMNB_STM TRUE FET_MEMNB_AOS TRA-N-CNL,SM,WDFN8,8.9 MOHM,30 V,24 A TRA-N-CNL,SM,WDFN8,10 MOHM,30 V,27 A TRA-N-CNL,SM,WDFN8,9 MOHM,30 V,12 A TRA-N-CNL,SM,WDFN8,8.8 MOHM,30 V,24 A TRA-N-CNL,SM,SO-8FL,3.1 MOHM,30 V,50 A TRA-N-CNL,SM,SO-8FL,3.5 MOHM,30 V,35 A TRA-N-CNL,SM,SO-8FL,4.5 MOHM,30 V,24 A TRA-N-CNL,SM,SO-8FL,3.6 MOHM,30 V,32 A C U5F3 IC TPS53819A 5 C 10 UF 10% 16 V X5R 805 D R5F15 249 KOHM 1% 2 CH 402 2 FT5U1 FTP FT5U2 FTP PGOOD 1 DRVH OUT VREG_PWRGPB_PWRGD 1 VBST DB5U1 VREG_NBCORE_ADDR 1VREG_NBCORE_ALERT_N 16 3 ADDR ALERT_N VREG_PWRGPB_EN 14 EN 11VREG_NBCORE_DH 4 1 13VREG_NBCORE_BST 69 26 IN 65 44 26 66 65 64 54 53 52 44 40 26 SMBUS_CLK SMBUS_DATA IN BI 1 2 VREG_NBCORE_OCP 1 R5F10 130 KOHM 1% 2 CH 402 TO INCREASE CURRENT LIMIT INCREASE TRIP RESISTOR VALUE 4 7 17 DB6F2 1 V_NBCORE 1 NOM.VOLTAGE: 1.25V V_NBCORE L5F1 SW SCL SDA DRVL B 2 FT4U2 FTP 0.1 UF 10% 25 V X7R 603 R5F12 47.5 KOHM 1% 2 CH 402 C5F5 1 12 VREG_NBCORE_SW 10 VREG_NBCORE_DL TRIP GND MPAD VO 5 VREG_NBCORE_VO FB 6 VREG_NBCORE_FB X869867-001 QFN17 Q5F2 NTMFS4985NF X866717-001 DFN5 FET 4 FREQUENCY = 400KHZ, SET OVER I2C SEE DATASHEET FOR REGISTER TABLE 1 TPS53819 I2C ADDRESS 0010 101 R/W HEX WRITE 0010 101 0 0X2A READ 0010 101 1 0X2B DB5F1 1000 PF 10% 50 V EMPTY 603 DB3T2 10 KOHM 1% CH 402 1 1 1 C6F9 820 UF 20% 2.5 V 2 POLY RDL 1 C6F12 820 UF 20% 2.5 V 2 POLY RDL 1 FTP FT4U1 1 B DB6F1 FTP FT4U3 C5F9 1 R5F9 1 2 400 NH IND A SM R5F18 1 42 0.00047 OHM 1 OHM 1% EMPTY 2 805 5 1 15 Q5F1 FET NTTFS4928N X862002-001 DFN5 C5F6 1 UF 10% 6.3 V X5R 69 26 57 51 402 1 2 3 1 VDD VREG 1 2 3 1 8 9 VREG_NBCORE_SW_R VREG_NBCORE_VCC VREG_NBCORE_LDO5 1 DB6F3 2 R5F7 ST3T3 1 2 0 OHM 5% 805 EMPTY 1 2 SHORT VENABLE R5F8 2 VREG_NPCORE_FB_R_GND 13.3 KOHM 1% 2 CH 402 SHORT A 1 ST3T4 A MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 50/72 2 CSA PAGE 50/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 VREGS, MEMCORE D D V_VREG_12P0_MEM_NBCORE 1 V_5P0 2 R5E30 1 2 V_MEMCORE 1 C5E14 4.7 UF 10% 6.3 V X5R 603 2 C 69 26 1 R5E25 1 R5E26 1 R5T15 0 OHM 5% 2 CH 402 0 OHM 5% 2 EMPTY 402 10 KOHM 5% 2 EMPTY 402 1 FTP FT5T4 2 VREG_PWRGPB_EN IN VREG_MEMCORE_VID1_R VREG_MEMCORE_VID0_R OUT R5E22 10 KOHM 5% 2 CH 402 1 1 EN 3 4 VID1 VID0 VCC VCCP 2 50 57 26 69 OUT C5E23 4.7 UF 10% 6.3 V X5R 603 FT5T5 FTP 1 C Q5E1 12 4 R5E27 10 KOHM 5% 2 CH 402 8 VREG_MEMCORE_SS PG 9 GH 14 VREG_MEMCORE_DH V_MEMCORE VREF RSET1 7 VREG_MEMCORE_SET0 R5E38 76.8 KOHM 1% 2 CH 402 1 6 V2 VREG_MEMCORE_SET2 5 V3 BST R5T7 1 2 15 VREG_MEMCORE_BST 2.2 OHM 1% CH 805 VREG_MEMCORE_BST_R 1 C5T12 2 0.1 UF 10% 25 V X7R 603 13 VREG_MEMCORE_SW 0.68 UH 15.5 A 0.005 OHM R5E43 VREG_MEMCORE_SW_S 1 2 Q5E2 NTTFS4939N 10 KOHM 1% CH 402 X863539-001 DFN5 1 R5E44 FET 1 OHM 2 RSET2 1 4 11 VREG_MEMCORE_DL CSP 16 VREG_MEMCORE_CSP IND SM 1 CSN 17 VREG_MEMCORE_CSN FB 10 21 R5E35 15.8 KOHM 1% 2 CH 402 PGND MPAD COMP 19 VREG_MEMCORE_FB 1 R5E42 15 KOHM 1% 2 CH 402 20 VREG_MEMCORE_COMP X862818-001 QFN20 RSET3 1 2 1 C6E15 1 C5U5 820 UF 2 2 22 UF 20% 6.3 V X7R 805 C6F2 22 UF 20% 6.3 V X7R 805 1 2 C5F1 22 UF 20% 6.3 V X7R 805 1 2 C5U6 C6F1 22 UF 20% 6.3 V X7R 805 22 UF 20% 6.3 V X7R 805 1 FTP FT5U3 1 1 DB5E2 DB3T3 1000 PF 10% 50 V EMPTY 603 DB3T1 1 R5E39 R5E34 18.7 KOHM 1% 2 CH 402 1 C5E15 2 VREG_MEMCORE_RNT_R 1 C5E18 R5E37 2 R5E36 1 2 35.7 KOHM1% CH 402 3300 PF 10% 50 V X7R 402 1 562 OHM 1% CH 402 R5E32 1 2 10 KOHM 1% CH 402 VREG_MEMCORE_S VREG_MEMCORE_FB_R 1 C5E17 1 2 0 OHM 5% 805 EMPTY 2 ST3T2 1 2 SHORT VENABLE 1500 PF 10% 50 V X7R 402 2 RSET4 A I306 I307 I305 ZZ408 I312 I302 I308 I309 ZZ409 I313 8 A 68 PF 5% 50 V NPO 402 1 R5E29 130 KOHM 1% 2 CH 402 7 MS_PART# Q5E1 Q5E1 Q5E1 Q5E1 Q5E2 Q5E2 Q5E2 Q5E2 6 MATL REF_DES X875319-001 X875313-001 X876425-001 X875316-001 X875318-001 X875314-001 X876423-001 X875315-001 FET FET FET FET FET FET FET FET B R5E40 1 DB5E3 20% 2.5 V POLY RDL 4.99 KOHM1% CH 402 1 C5E25 2 ST5E2 IS OUTPUT VOLTAGE SENSE RETURN PLACE NEAR ST1002 AND CONNECT TO GND PLANE C5E20 0.1 UF 10% 25 V X5R 402 1% 2 EMPTY 805 1 2 3 0.1 UF 10% 6.3 V X5R 402 SHORT ST3T1 C5E19 GL_FSET VREG_MEMCORE_SW_R 2 FBRTN 1 1 DB6E3 L5E1 1 2 1 SW 18 FTP FT4T5 1 V1 VREG_MEMCORE_SET1 VREG_MEMCORE_RTN B 1 DB5E1 VREG_PWRGPB_PWRGD VR_MM 1 1 FT5T7 FTP FET NTTFS4928N X862002-001 DFN5 1 2 3 1 1 U5E2 IC NCP5269 SHORT R5E12 10 KOHM 5% 2 EMPTY 402 DUAL SETPOINT VR V_HI = 1.25V V_LO = 0.95V 2 1 2 VREG_VDDR_VCC5 2.2 OHM 1% CH 402 V_SOC1P8 2 ST5E4 V_SOC1P8 2 10 UF 10% 16 V EMPTY 805 1 IN VREG_MEMCORE_VID0 1 C5T9 10 UF 10% 16 V EMPTY 805 SHORT IN 1 C5E22 2 8 C5E21 10 UF 10% 16 V X5R 805 ST5E3 8 VREG_MEMCORE_VID1 1 C5T10 10 UF 10% 16 V X5R 805 5 IN 5 43 TRA-N-CNL,SM,WDFN8,8.9 MOHM,30 V,24 A TRA-N-CNL,SM,WDFN8,10 MOHM,30 V,27 A TRA-N-CNL,SM,WDFN8,9 MOHM,30 V,12 A TRA-N-CNL,SM,WDFN8,8.8 MOHM,30 V,24 A TRA-N-CNL,SM,WDFN8,6.3 MOHM,30 V,24 A TRA-N-CNL,SM,WDFN8,5.4 MOHM,30 V,27 A TRA-N-CNL,SM,WDFN8,4.5 MOHM,30 V,17 A TRA-N-CNL,SM,WDFN8,5 MOHM,30 V,30 A 5 NOTE: FSEL RES (R1127) 2K 6K 15K TRUEDESCR. BOM PROPERTY FET_MEMNB_IRF TRUE FET_MEMNB_TOS TRUE FET_MEMNB_STM TRUE FET_MEMNB_AOS TRUE FET_MEMNB_IRF TRUE FET_MEMNB_TOS TRUE FET_MEMNB_STM TRUE FET_MEMNB_AOS 4 MICROSOFT CONFIDENTIAL 3 FSW 300KHZ 400KHZ 600KHZ PROJECT NAME PAGE GREYBULL_RETAIL 51/72 2 CSA PAGE 51/72 1 FAB REV M 1.0 8 7 6 5 D 4 3 2 1 D VREG, MEMIOCD 43 IN V_VREG_12P0_MEM_NBCORE R6C4 2 1 2.2 OHM 1% CH 402 1 C5P1 1 C5C5 1 C5C4 2 2 2 2 10 UF 10% 16 V X5R 805 10 UF 10% 16 V X5R 805 1 C6C4 1 UF 10% V 2 16 X7R 805 10 UF 10% 16 V EMPTY 805 10 UF 10% 16 V EMPTY 805 C U6C1 IC TPS53819A 5 C 1 C5P2 R5C10 249 KOHM 1% 2 CH 402 15 PGOOD DRVH 26 56 53 VREG_PWRGPA_PWRGD OUT FT5P4 FTP FT5P3 FTP 1 VDD VREG 1 VBST 1 DB6C2 1 VREG_MEMIOCD_ADDR VREG_MEMIOCD_ALERT_N 16 3 ADDR ALERT_N VREG_PWRGPA_EN 14 EN 11 VREG_MEMIOCD_DH 4 13 VREG_MEMIOCD_BST 69 26 IN 65 44 26 66 65 64 54 53 50 44 40 26 B SMBUS_CLK SMBUS_DATA IN BI 1 2 SW SCL SDA DRVL VREG_MEMIOCD_OCP 1 R6C11 4 2 TO INCREASE CURRENT LIMIT INCREASE TRIP RESISTOR VALUE 1 V_MEMIOCD NOM.VOLTAGE: 1.5V 1 DB6B1 V_MEMIOCD L5C1 1 2 12 VREG_MEMIOCD_SW 10 VREG_MEMIOCD_DL GND MPAD FB 5 6 VREG_MEMIOCD_VO X869867-001 QFN17 4 TPS53819 I2C ADDRESS 0011 001 R/W HEX WRITE 0011 001 0 0X32 READ 0011 001 1 0X33 R6C8 1 2 10 KOHM 1% CH 402 1 1 IND SM 1 1 C6C14 820 UF 20% 2.5 V 2 POLY RDL 2 1 C6C2 1 1000 PF 10% 50 V EMPTY 603 FREQUENCY = 400KHZ, SET OVER I2C SEE DATASHEET FOR REGISTER TABLE DB6C1 1 UH R6C2 1 13.9 A 1 OHM 0.003 OHM 1% EMPTY 2 805 Q5C2 NTTFS4939N X863539-001 DFN5 FET VREG_MEMIOCD_FB 1 2 3 100 KOHM 1% 2 CH 402 C5C10 TRIP VO 7 17 1 FT4N2 FTP 0.1 UF 10% 25 V X7R 603 R5C11 105 KOHM 1% 2 CH 402 Q5C1 FET NTTFS4928N X862002-001 DFN5 5 1 1 C6C13 1 UF 10% V 2 16 X5R 69 603 8 9 VREG_MEMIOCD_SW_R VREG_MEMIOCD_LDO5 1 2 3 VREG_MEMIOCD_VCC 1 2 1 R6C10 1 22 UF 20% 6.3 V EMPTY 805 1 B DB6C4 1 DB3P1 FTP FT4N1 DB6B2 DB3P2 DUPLICATE TEST POINTS FOR PROBING AT VR SOURCE+SINK ST7C1 1 2 0 OHM 5% 805 EMPTY C6B10 FTP FT4N4 2 SHORT VENABLE 1 R6C9 6.65 KOHM 1% 2 CH 402 I296 ZZ404 I303 I294 I298 I293 FET FET FET FET FET FET FET FET TRA-N-CNL,SM,WDFN8,8.9 MOHM,30 V,24 A TRA-N-CNL,SM,WDFN8,10 MOHM,30 V,27 A TRA-N-CNL,SM,WDFN8,9 MOHM,30 V,12 A TRA-N-CNL,SM,WDFN8,8.8 MOHM,30 V,24 A TRA-N-CNL,SM,WDFN8,6.3 MOHM,30 V,24 A TRA-N-CNL,SM,WDFN8,5.4 MOHM,30 V,27 A TRA-N-CNL,SM,WDFN8,4.5 MOHM,30 V,17 A TRA-N-CNL,SM,WDFN8,5 MOHM,30 V,30 A TRUEDESCR. BOM PROPERTY FET_MEMNB_IRF TRUE FET_MEMNB_TOS TRUE FET_MEMNB_STM TRUE FET_MEMNB_AOS TRUE FET_MEMNB_IRF TRUE FET_MEMNB_TOS TRUE FET_MEMNB_STM TRUE FET_MEMNB_AOS A 1 ST7C2 ZZ405 I302 MATL REF_DES X875319-001 X875313-001 X876425-001 X875316-001 X875318-001 X875314-001 X876423-001 X875315-001 SHORT I295 MS_PART# Q5C1 Q5C1 Q5C1 Q5C1 Q5C2 Q5C2 Q5C2 Q5C2 2VREG_MEMIOCD_FB_R_GND A I297 MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 52/72 2 CSA PAGE 52/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 D D VREG, MEMIOAB 43 IN V_VREG_12P0_MEM_NBCORE R1U3 1 2 2.2 OHM 1% CH 402 1 C1U2 1 C1U3 1 C9F3 2 2 2 2 10 UF 10% 16 V X5R 805 10 UF 10% 16 V X5R 805 1 C9F8 1 UF 10% V 2 16 X7R 805 10 UF 10% 16 V EMPTY 805 10 UF 10% 16 V EMPTY 805 C U9F2 IC TPS53819A 5 C 1 C9F4 OUT 15 PGOOD FT1U1 FTP 1 VBST 1 DB9F2 VREG_MEMIOAB_ADDR 1 VREG_MEMIOAB_ALERT_N 16 3 ADDR ALERT_N 14 EN 11 VREG_MEMIOAB_DH 4 69 26 VREG_PWRGPA_EN IN 65 44 26 66 65 64 54 52 50 44 40 26 IN BI SMBUS_CLK SMBUS_DATA 1 2 SW SCL SDA 1 R9F12 TRIP 7 17 GND MPAD 2 TO INCREASE CURRENT LIMIT INCREASE TRIP RESISTOR VALUE FT1U3 FTP VO FB R9F1 1 10 VREG_MEMIOAB_DL 6 VREG_MEMIOAB_VO VREG_MEMIOAB_FB X869867-001 QFN17 FREQUENCY = 400KHZ, SET OVER I2C SEE DATASHEET FOR REGISTER TABLE R9F10 1 2 10 KOHM 1% CH 402 1 V_MEMIOAB 1 IND SM 1 1 C9E11 820 UF 20% 2.5 V 2 POLY RDL 2 1 C9F2 1 1 2 1 1000 PF 10% 50 V EMPTY 603 TPS53819 I2C ADDRESS 0011 000 R/W HEX WRITE 0011 000 0 0X30 READ 0011 000 1 0X31 1 UH 13.9 A 0.003 OHM 1 OHM 1% EMPTY 2 805 Q9F1 NTTFS4939N X863539-001 DFN5 FET 4 DB9F1 NOM.VOLTAGE: 1.5V L9E3 1 2 12 VREG_MEMIOAB_SW 5 V_MEMIOAB 1 1 DB9F7 1 2 3 100 KOHM 1% 2 CH 402 4 C9F7 0.1 UF 10% 25 V X7R 603 DRVL VREG_MEMIOAB_OCP 1 13 VREG_MEMIOAB_BST R9F11 90.9 KOHM 1% 2 CH 402 Q9F2 FET NTTFS4928N X862002-001 DFN5 VREG_VDDIOCD_SW_R B VREG_PWRGPA_PWRGD DRVH 56 52 69 26 FT1U2 FTP 1 VDD VREG 1 2 3 R9F6 249 KOHM 1% 2 CH 402 8 9 5 1 1 C9F6 1 UF 10% V 2 16 X5R 603 VREG_MEMIOAB_VCC VREG_MEMIOAB_LDO5 R9F13 1 2 0 OHM 5% 805 EMPTY 22 UF 20% 6.3 V EMPTY 805 1 B DB9F3 1 DB3U1 FTP FT1U5 DB9F4 DB3U2 DUPLICATE TEST POINTS FOR PROBING AT VR SOURCE+SINK ST7F1 1 C9F21 FTP FT1U4 2 SHORT VENABLE 1 R1U5 6.65 KOHM 1% 2 CH 402 I295 ZZ406 I302 I293 I297 I292 FET FET FET FET FET FET FET FET TRA-N-CNL,SM,WDFN8,8.9 MOHM,30 V,24 A TRA-N-CNL,SM,WDFN8,10 MOHM,30 V,27 A TRA-N-CNL,SM,WDFN8,9 MOHM,30 V,12 A TRA-N-CNL,SM,WDFN8,8.8 MOHM,30 V,24 A TRA-N-CNL,SM,WDFN8,6.3 MOHM,30 V,24 A TRA-N-CNL,SM,WDFN8,5.4 MOHM,30 V,27 A TRA-N-CNL,SM,WDFN8,4.5 MOHM,30 V,17 A TRA-N-CNL,SM,WDFN8,5 MOHM,30 V,30 A TRUEDESCR. BOM PROPERTY FET_MEMNB_IRF TRUE FET_MEMNB_TOS TRUE FET_MEMNB_STM TRUE FET_MEMNB_AOS TRUE FET_MEMNB_IRF TRUE FET_MEMNB_TOS TRUE FET_MEMNB_STM TRUE FET_MEMNB_AOS A 1 ST7F2 ZZ407 I301 MATL REF_DES X875319-001 X875313-001 X876425-001 X875316-001 X875318-001 X875314-001 X876423-001 X875315-001 SHORT I294 MS_PART# Q9F2 Q9F2 Q9F2 Q9F2 Q9F1 Q9F1 Q9F1 Q9F1 VREG_MEMIOAB_FB_R_GND I296 2 A MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 53/72 2 CSA PAGE 53/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 VREGS, V5P0 D D 43 V_VREG_12P0_TO_5P0_3P3 IN 1 2 1 C6T17 10 UF 10% 16 V X5R 805 2 C3E12 10 UF 10% 16 V X5R 805 1 C4E4 10 UF 10% 16 V X5R 805 2 1 2 C7T2 10 UF 10% 16 V X5R 805 R3E23 1 2 VREG_5P0_VDD 2.2 OHM 1% CH 1 402 C3E13 1 UF 10% 16 V 2 X7R 603 U3E2 IC TPS53819A 249 KOHM 1% 2 CH 402 1 2 C3E16 FT7T3 FTP 1 UF 10% 16 V X7R 603 69 26 10 KOHM 5% 2 CH 402 VREG_V5P0_PWRGD 1 OUT DB3E4 R3E18 15 1 61.9 KOHM FT7T4 FTP 1% 69 26 IN 2 CH 402 1 R3E22 VREG_V5P0_EN 65 10 KOHM 44 26 66 5% 50 44 40 26 2 CH 65 64 53 52 IN BI 2 V_5P0 DB3F5 12 VREG_5P0_SW 1 10 VREG_5P0_DL GND MPAD VO 5 VREG_5P0_VO FB 6 VREG_5P0_FB 4 1 2 3 X869867-001 QFN17 DB3E3 1 1 1.5 UH IND 11.1 A SM 0.00475 OHM 1 R3E25 Q3E1 1 OHM 1% NTTFS4939N X863539-001 2 EMPTY 402 DFN5 VREG_5P0_SW_R FET 1 C3E17 0.01 UF 10% 16 V 2 EMPTY 402 I114 I109 ZZ414 I122 ZZ451 I121 TRA-N-CNL,SM,WDFN8,5.4 MOHM,30 V,27 A TRA-N-CNL,SM,WDFN8,4.5 MOHM,30 V,17 A TRA-N-CNL,SM,WDFN8,5 MOHM,30 V,30 A TRA-N-CNL,SM,WDFN8,6.3 MOHM,30 V,24 A TRA-N-CNL,SM,WDFN8,5.4 MOHM,30 V,27 A TRA-N-CNL,SM,WDFN8,4.5 MOHM,30 V,17 A TRA-N-CNL,SM,WDFN8,5 MOHM,30 V,30 A 2VREG_5P0_FB_R_GND TRUEDESCR. BOM PROPERTY FET_5P0_IRF TRUE FET_5P0_TOS TRUE FET_5P0_STM TRUE I115 FET_5P0_AOS I117 TRUE FET_5P0_IRF I116 FET_5P0_TOS FET_5P0_STM TRUE FET_5P0_AOS 1 2 0 OHM 5% 805 EMPTY 2 C3E8 22 UF 20% 6.3 V X7R 805 6 22 UF 20% 6.3 V X7R 805 C3E10 22 UF 20% 6.3 V X7R 805 1 FTP FT7U2 1 DB3F6 1 DB3F7 B 2 SHORT VENABLE 5.6 PF 0.5PF 50 V NPO 402 A MICROSOFT CONFIDENTIAL 7 C3E9 ST4B1 1 [PAGE_TITLE=VREGS, V5P0] 8 C3E15 820 UF 20% 6.3 V POLY TH FT7T5 SHORT TRA-N-CNL,SM,WDFN8,6.3 MOHM,30 V,24 A ST3E1 FET FET FET FET FET FET FET FET R3E16 1 2 7.5 KOHM 1% CH 402 C3E2 1 2 1 FTP 1 A MATL REF_DES X875318-001 X875314-001 X876423-001 X875315-001 X875318-001 X875314-001 X876423-001 X875315-001 R3E21 1 KOHM 1% 2 CH 402 TPS53819 I2C ADDRESS 0010 110 R/W HEX WRITE 0010 110 0 0X2C READ 0010 110 1 0X2D MS_PART# Q3E2 Q3E2 Q3E2 Q3E2 Q3E1 Q3E1 Q3E1 Q3E1 VOLTAGE: 5.09V 1 L3E1 SW R3E19 I110 V_5P0 1 FT7U1 FTP TRIP 7 17 90.9 KOHM 1% 2 CH 402 C3E14 0.1 UF 10% 25 V X7R 603 SCL SDA 4 R3E17 1 EN 1 2 VREG_5P0_OCP B 13 VREG_5P0_BST DRVL 402 1 VBST 4 ADDR ALERT_N 14 SMBUS_CLK SMBUS_DATA 11 VREG_5P0_DH PGOOD 16 3 VREG_5P0_ADDR 1 VREG_5P0_ALERT_N DRVH Q3E2 NTTFS4939N X863539-001 DFN5 FET 1 2 3 R3E20 VDD VREG R7T4 1 1 1 C 5 8 9 VREG_5P0_LDO5 5 C 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 54/72 2 CSA PAGE 54/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 VREGS, V5P0 DUAL D D R4B13 VREG_V5P0DUAL_CDG 1 V_5P0STBY 1 V_5P0STBY V_12P0 1 C 1 R6N1 1 R4B11 10 KOHM 5% 2 CH 402 10 KOHM 5% 2 CH 402 2 C4B11 0.22 UF 10% 10 V X7R 603 2 1 UF 10% 10 V X5R 402 R4B14 2 VREG_V5P0_SEL_PGATE 10 KOHM 402 1% CH VREG_V5P0_SEL_NGATE 1 1 VREG_V5P0_DUAL_SEL0 IN 1 R4B8 FT6N3 FTP 1 2 VREG_V5P0_SEL_B1 2 VREG_V5P0_SEL_B2 4.75 KOHM 1% CH 402 4 10 KOHM 5% 2 CH 402 1 XSTR 3 4 VREG_V5P0_SEL_PGATE_R 1 C4B1 0.22 UF 10% 6.3 V EMPTY 402 1 2 D<3> D<2> D<1> D<0> C4B3 4.7 UF 10% 16 V X5R 1206 V_5P0 2 1 C V_5P0DUAL S2 G2 V_5P0DUAL 5 8 7 6 NOM.VOLTAGE: 5.00V 1 G1 S1 1 X801132-002 1 R4B7 4.75 KOHM 1% 2 CH 402 1 FTP FT6N1 DB4B6 DB4B7 5 26 6 5 2 0 OHM 5% 402 CH 2 U4B3 R4B10 IC SI4501DY 1 3 2 C4B4 220 UF 20% 10 V ELEC RDL U4B4 R4B9 VREG_V5P0_SEL_C 1 C4B2 2 100 OHM1% 402 CH Q6N1 NTTFS4939N X863539-001 DFN5 FET 4 B 1 2 3 B VREG_V5P0_DUAL_SEL0 VREG_5P0_SEL NGATE/PGATE V_5P0DUAL HIGH LOW V_5P0STBY LOW HIGH V_5P0 A A DRAWING [PAGE_TITLE=VREGS, V5P0 DUAL] 8 7 Tue Jun 18 16:42:27 2013 6 5 4 3 MICROSOFT CONFIDENTIAL PROJECT NAME PAGE GREYBULL_RETAIL 55/72 2 CSA PAGE 55/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 VREGS, V3P3 D D 43 IN V_VREG_12P0_TO_5P0_3P3 1 2 C4F2 10 UF 20% 16 V X5R 1206 1 C6T20 10 UF 20% 16 V X5R 1206 2 1 2 C6U2 10 UF 20% 16 V X5R 1206 C4E10 10 UF 20% 16 V X5R 1206 1 2 C4E11 10 UF 20% 16 V X5R 1206 C C 1 R4F6 0 OHM 5% 2 CH 402 VREG_3P3_VIN2 1 2 69 26 1 2 VIN1 VIN2 1 UF 10% 16 V X5R 603 VREG_V3P3_SS B 13 14 C4F3 VREG_PWRGPA_EN IN DB4F5 U4F1 IC TPS54526 7 4 EN SS FT6U4 FTP V_3P3 1 VOLTAGE: 3.3V L4F1 SW1 SW2 10 VREG_V3P3_VSW 11 VBST 12 VREG_V3P3_BST 1 1 C4F5 1 VFB 2 VREG_V3P3_FB PG VREG5 6 3 VREG_PWRGPA_PWRGD VREG_V3P3_VREG OUT 2 1.5 UH 4.95 A 0.0156 OHM 2 0.1 UF 10% 25 V X7R 603 VO PGND1 PGND2 GND MPAD V_3P3 1 IND SM 1 VREG_V3P3_VO R4F25 100 OHM 5% 2 CH 1206 1 52 53 26 69 1 8 9 5 15 1 2 102 K 1% CH 402 R4F5 1 2 0 OHM 5% 805 EMPTY ST4F3 1 2 FTP FT6U1 1 C4E14 R4F4 DB3R1 22 UF 20% 6.3 V EMPTY 805 C4E13 22 UF 20% 6.3 V EMPTY 805 C6U3 22 UF 20% 6.3 V X7R 805 C4F7 22 UF 20% 6.3 V X7R 805 C4F8 22 UF 20% 6.3 V X7R 805 DB4F1 C4F21 C6U4 470 UF 20% 6.3 V POLY TH 22 UF 20% 6.3 V X7R 805 SHORT 1 X865085-001 TSSOP15 1 VENABLE R4F8 FTP FT5U4 1 B DB5F2 30.1 KOHM 1% 2 CH 402 C4F6 0.022 UF 10% 16 V X7R 402 1 2 C4F4 1 UF 10% 16 V X7R 603 A A [PAGE_TITLE=VREGS, V3P3] 8 7 MICROSOFT CONFIDENTIAL 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 56/72 2 CSA PAGE 56/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 VREGS, VSOCPHY D D V_SOCPHY C C NOM.VOLTAGE: 0.95V FT6U5 FTP DB4F7 1 1 V_3P3 1 2 1 C4F14 1 UF 10% 6.3 V X5R 402 2 C4F15 10 UF 20% 6.3 V X5R 805 1 2 3 C4F16 10 UF 20% 6.3 V EMPTY 805 VCC VIN L4F2 SW1 SW2 FB 51 50 69 26 OUT 9 VREG_PWRGPB_PWRGD IN VREG_PWRGPB_EN 10 1 EN 2 1.5 UH 2.6 A VREG_SOCPHY_FB NC GND1 GND2 MPAD 1 IND SM 1 PGOOD B 69 26 1 6VREG_SOCPHY_SW 7 R4F16 4.7 KOHM 5% 2 EMPTY 402 8 4 5 11 X865086-001 DFN11 1 2 C4F12 22 UF 20% 6.3 V X7R 805 R4F18 1 C4F13 22 UF 20% 6.3 V X7R 805 2 R4F24 182 OHMS 1% 2 EMPTY 603 1 C4F17 10 UF 20% 6.3 V X5R 805 B C4F11 2200 PF 10% 50 V EMPTY 402 C4F10 1 2 220 PF 5% 50 V NPO R4F14 402 1 2 47.5 KOHM 1% CH 402 1 FTP FT6U2 0.04 OHM VREG_SOCPHY_COMP_C 2 V_SOCPHY U4F3 IC RT8071A 1 1 1 R4F10 1 2 0 OHM 5% 805 EMPTY DB4F2 FTP FT6U3 DB4F6 ST4F4 VREG_SOCPHY_FB_TOP 2 1 SHORT VENABLE 82.5 KOHM 1% 2 CH 402 A A MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 57/72 2 CSA PAGE 57/72 1 FAB REV M 1.0 8 7 6 5 4 3 VREGS, VSOCPLL + VBURN + 2 1 VFUSE + VBAT V_BURN V_BURN NOM.VOLTAGE: 1.9V D 2 V_3P3 1 2 R6C14 4.7 KOHM 5% 2 EMPTY 402 V_1P8STBY V_BAT 1 NOM.VOLTAGE: 1.8V R6R21 V_BAT VREG_BURN_EN_R 2 R6R20 4.99 KOHM 1% 2 EMPTY 402 C I171 8 C6C5 1 UF 10% 6.3 V X5R 402 1 2 5% CH 1 1 0 OHM 402 1 VOUT VIN I169 0 OHM 5% 2 CH 402 R6C13 1 IC U6C3 CAT6219 3 R6C15 10 KOHM 5% 2 CH 402 EN ADJ 4 GND 2 X865083-001 SOT23-5 2 DB5C2 2 1 1 UF 10% 6.3 V EMPTY 402 2 C6C101 1 UF 10% 6.3 V X5R 402 DB6C3 1 SOT23 X857156-001 2 C6D11 0.047 UF 10% 10 V X7R 402 1 2 C6C9 10 UF 10% 6.3 V X5R 805 1 1 C6C6 0.1 UF 10% 6.3 V EMPTY 402 2 D R3R1 1 KOHM 1% 2 CH 402 R6D39 1 R6D38 5.49 KOHM 1% 2 CH 402 R6C19 887 OHM 1% 2 CH 402 1 1 2 100 OHM 1% CH 402 VREG_BURN_OUT_CGD C VREG_BURN_ADJUST 1 FT5P6 FTP 1 UF 10% 6.3 V EMPTY 402 C6C8 1 U6C6 FET VREG_BURN_OUT_G 1 R6C22 1 OHM 1% 2 CH 402 VREG_BURN_EN IN C6C7 VREG_BURN_OUT 5 VREG_BURN_COUT 1 I170 1 3 C6D1 4.7 UF 10% 6.3 V X5R 603 1 R6C16 1.65 KOHM 1% 2 CH 402 NOTE: BOTTOM ADJUST RESISTOR LEFT IN TO REDUCE EFFECT OF ADJUST PIN CURRENT WHEN USED WITH 1K DIGIPOT 1 1 V_SOC1P8 V_SOC1P8 NOM.VOLTAGE: 1.83V 1 B 1 2 1 C5C19 1 UF 10% 6.3 V EMPTY 402 DB5D3 B C5C20 1 UF 10% 6.3 V EMPTY 402 2 1 1 FTP FT5R4 FTP FT5R5 V_3P3 1 DB5D2 NOTE: THIS WAS SET TO 1.83V TO ACCOMODATE DROP IN FERRITES V_3P3 1 2 C5C23 1 UF 10% 6.3 V X5R 402 2 1 2 FTP FT5P5 V_FUSE C6D5 NOM.VOLTAGE: 0.95V V_FUSE 1 UF 10% 6.3 V X5R 402 ADJUST/GND 1 X819037-001 1.8V VREG_SOC1P8_ADJUST R5C20 1 OHM 1% 2 CH 402 1 2 R5C19 200 OHM 1% 2 CH 603 1 2 C5C18 0.1 UF 10% 6.3 V EMPTY 402 1 2 VIN1 VIN2 7 8 VOUT1 VOUT2 69 26 DB6D3 4 VREG_PWRGPB_EN IN 1 5 EN CBYP ADJ 6 GND MPAD 3 9 X865082-001 DFN9 I178 7 FTP FT4R1 R6D8 1 OHM 1% 2 CH 402 1 C6D3 1 UF 10% 6.3 V X5R 402 DB6D2 C6D4 1 UF 10% 6.3 V X5R 402 1 1 DB3R2 R6D10 2.74 KOHM 1% 2 CH 402 A VREG_FUSE_ADJ C5C21 4.7 UF 10% 6.3 V X5R 603 R5C15 100 OHM 1% CH 402 1 2 C6D6 1 0.01 UF 10% 16 V EMPTY 402 2 NOTE: BOTTOM ADJUST RESISTOR LEFT IN TO REDUCE EFFECT OF ADJUST PIN CURRENT WHEN USED WITH 1K DIGIPOT 8 1 1 A 1 U6D1 IC CAT6241 VREG_FUSE_COUT 1 OUT DB5D1 VREG_FUSE_CBYP 1 IN 1 VREG_SOC1P8_COUT 3 U5C3 IC NCP1117 6 1 4.7 UF 10% 6.3 V X5R 603 MICROSOFT CONFIDENTIAL 5 4 3 R6D11 3 KOHM 1% 2 CH 402 I176 C6D2 PROJECT NAME PAGE GREYBULL_RETAIL 58/72 2 CSA PAGE 58/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 VREGS, VSB2P5 D D V_SB2P5 C C NOM.VOLTAGE: 2.5V V_5P0 1 2 1 C3E4 1 UF 10% 6.3 V X5R 402 2 C4B13 10 UF 20% 6.3 V X5R 805 1 2 B 3 100 KOHM 1% 2 CH 402 C4B12 10 UF 20% 6.3 V X5R 805 R3D3 1 R3D4 9 VREG_VSB2P5_PWRGD 10 KOHM 5% 2 CH 402 VREG_VSB2P5_EN 1 2 10 VCC VIN L3D1 SW1 SW2 6 7 FB 1 1 VREG_SB2P5_SW NC GND1 GND2 MPAD 4.7 UF 10% 6.3 V EMPTY 603 1 2 R3E4 C3D1 22 UF 20% 6.3 V X7R 805 1 C3D2 22 UF 20% 6.3 V X7R 805 2 R3D1 182 OHMS 1% 2 EMPTY 603 1 C3D3 10 UF 20% 6.3 V X5R 805 B C3E3 2200 PF 10% 50 V EMPTY 402 C3E1 1 2 220 PF 5% 50 V NPO 402 1 1 1 R3D5 1 2 47.5 KOHM 1% CH 402 1 FTP FT7R10 0.04 OHM 4.7 KOHM 5% 2 EMPTY 402 8 4 5 11 X865086-001 DFN11 C3D4 1 IND SM 1 PGOOD EN 2 1.5 UH 2.6 A VREG_SB2P5_FB VREG_SB2P5_COMP_C 2 1 V_SB2P5 U3D5 IC RT8071A R3D2 1 2 0 OHM 5% 805 EMPTY DB3D2 FTP FT7R9 DB3D1 ST3D1 VREG_SB2P5_TOP 2 1 SHORT VENABLE R3E2 15 KOHM 1% 2 CH 402 A A MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 59/72 2 CSA PAGE 59/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 VREGS, VSB1P8PLL + VSB1P8IO + VSBCORE + VSB1P1PLL D D 1 2 1 C7T8 1 UF 10% 6.3 V EMPTY 402 2 V_SB1P8 C7T7 NOM.VOLTAGE: 1.83V 1 UF 10% 6.3 V EMPTY 402 V_SB1P8 FT7T6 FTP 1 1 2 C 26 4 10 KOHM 5% 2 EMPTY 402 C7T4 1 UF 10% 6.3 V X5R 402 R7T7 IN 5 VREG_SB1P8_EN IC U3E1 CAT6243DC DB3E5 VIN VOUT 2 EN ADJ GND1 GND2 1 3 6 0.1 UF 10% 16 V EMPTY 603 1 1 FTP FT7T2 1 1 1 1 1 R7T8 1 OHM 1% 2 CH 402 X854310-001 DPAK-6 C7T6 1 DB3E2 FTP FT1U7 DB3D10 FTP FT7T1 DB3E1 R3E10 1.47 KOHM 1% CH 402 C VREG_SB1P8_COUT V_SB2P5 NOTE: THIS WAS SET TO 1.83V TO ACCOMODATE DROP IN FERRITES 1 1 R7T2 10 KOHM 5% 2 CH 402 VREG_SB1P8_ADJUST 1 2 R3E11 1.15 KOHM 1% CH 402 C7T5 4.7 UF 10% 6.3 V X5R 603 1 B NOTE: BOTTOM ADJUST RESISTOR LEFT IN TO REDUCE EFFECT OF ADJUST PIN CURRENT WHEN USED WITH 1K DIGIPOT 2 C7R13 1 UF 10% 6.3 V EMPTY 402 1 2 C7R12 1 1 UF 10% 6.3 V EMPTY 402 V_SB2P5 2 C7R14 1 UF 10% 6.3 V X5R 402 R7R3 10 KOHM 5% 2 CH 402 VREG_SB1P1_EN 1 2 C7R15 4 1 1 1 VIN VOUT 2 EN ADJ GND1 GND2 1 3 6 1 5 B 1 1 OHM 1% 2 CH 402 X854310-001 DPAK-6 0.1 UF 10% 16 V EMPTY 603 DB3D5 1 FTP FT7R8 1 FTP FT7R3 DB3D11 R7R5 VREG_SB1P1_COUT 1 FTP FT7R4 NOM.VOLTAGE: 1.1V DB3D9 U3D3 IC CAT6243DC DB3D4 V_SB1P1 FT7R7 FTP 1 1 V_SB1P1 R3D19 825 OHMS 1% CH 402 VREG_SB1P1_ADJUST A A 1 2 C3D17 0.1 UF 10% 6.3 V EMPTY 402 1 2 C7R11 4.7 UF 10% 6.3 V X5R 603 R7R4 2 KOHM 1% CH 402 NOTE: BOTTOM ADJUST RESISTOR LEFT IN TO REDUCE EFFECT OF ADJUST PIN CURRENT WHEN USED WITH 1K DIGIPOT 8 7 6 5 4 3 MICROSOFT CONFIDENTIAL PROJECT NAME PAGE GREYBULL_RETAIL 60/72 2 CSA PAGE 60/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 VREGS,STANDBY SWITCHERS 3P3 D 1 VREG_3P3STBY_IN_SEL VREG_3P3STBY_IN_SEL NGATE/PGATE VREG_3P3STBY_VCC HIGH LOW V_5P0STBY LOW HIGH V_5P0 D V_12P0 61 61 IN V_VREG_STBY_VIN V_VREG_STBY_VIN IN 1 2 1 R7N1 1 R3B1 10 KOHM 5% 2 CH 402 10 KOHM 5% 2 CH 402 C7N1 0.22 UF 10% 6.3 V X5R 402 1 2 C3B1 220 UF 20% 10 V ELEC RDL SI4501DY 3 4 R7P1 1 61 V_VREG_STBY_VIN IN 10 KOHM 402 VREG_3P3STBY_IN_SEL_C 1 IN 1% CH R7N2 U7P1 3 R7P2 C VREG_3P3STBY_IN_SEL_PGATE 1 VREG_3P3STBY_IN_SEL FT7P2 FTP 2 VREG_3P3STBY_IN_SEL_B1 C3B2 0.22 UF 10% 6.3 V EMPTY 402 1 6 5 1 2 C3C1 22 UF 20% 10 V EMPTY 1206 V_5P0 2 1 V_VREG_3P3STBY_IN 5 8 7 6 D<3> D<2> D<1> D<0> NOM.VOLTAGE: 5.00V 1 FTP G1 S1 FT7P1 I288 DB3C7 1 2 VREG_3P3STBY_IN_SEL_B2 X801132-002 4.75 KOHM 1% CH 402 1 S2 G2 VREG_3P3STBY_IN_SEL_NGATE 2 4.7 KOHM 5% 2 CH 402 26 2 IC U3C1 4 1 1 1 R7P3 XSTR C DB3C8 4.75 KOHM 1% 2 CH 402 V_5P0STBY L4C1 2.2 UH 1.6 A 0.08DCR V_VREG_3P3STBY_IN 2 IND 1210 OUT 61 62 V_3P3STBY V_VREG_STBY_VIN 1 NOM.VOLTAGE: 3.315V MAX RECOMMENDED CURRENT: 1A CR4C1 FT7P4 FTP 1 1 2 1 2 16 C3C3 2 10 UF 20% 6.3 V X5R 805 1 C7P3 1 R3C2 100 KOHM 1% 2 EMPTY 402 1 2 1 UF 10% 6.3 V X5R 402 A EN 14 PWRGD 8 9 FTP FT7P10 BOOST RT/CLK SS VSENSE COMP GND1 GND2 AGND MPAD VREG_3P3STBY_EN 1 R7P5 0 OHM 5% 2 CH 402 10 UF 20% 6.3 V X5R 805 C3C4 VREG_3P3STBY_PWRGD 2 10 UF 20% 6.3 V EMPTY 805 C3C11 1 2 1 2 15 1 1 2 C7P1 4.7 UF 10% 6.3 V X5R 603 R7P4 20 KOHM 1% 2 CH 402 FT7P5 FTP 1 C3C2 0.1 UF 10% 16 V X7R 603 6 VREG_3P3STBY_FB 7 VREG_3P3STBY_COMP 3 4 1 5 C3C6 0.012 UF 17 10% 1 C3C8 16 V 2 X7R 100 PF 5% 402 50 V 2 NPO 402 1 13 1.5 UH 2.6 A 0.04 OHM 2 1 IND SM 1 0.05 OHM VREG_3P3STBY_BT 1 2 R3C6 C4C5 C6P2 10 UF 20% 6.3 V X5R 805 10 UF 20% 6.3 V X5R 805 1 2 93.1 KOHM1% CH 402 1 R3C7 C3C7 1 2 470 PF 5% 50 V NPO 402 30.1 KOHM 1% 2 CH 402 R3C10 C4C6 22 UF 20% 6.3 V X7R 805 1 R3C9 1 2 0 OHM 5% 402 EMPTY C6P3 1 C4C8 10 UF 20% 6.3 V X5R 805 DB4C1 FTP FT6P1 10 UF 20% 6.3 V X5R 805 FTP FT6P3 DB4C4 ST4C3 VREG_3P3STBY_FB_TOP 2 1 VENABLE SHORT 21.5 KOHM 1% 2 CH 402 1 1 R3C8 90.9 KOHM 1% 2 CH 402 1 2 A VREG_3P3STBY_AGND C3C5 1500 PF 10% 50 V X7R 402 1 V_1P8STBY X865747-001 QFN17 10 VREG_3P3STBY_SW 11 12 SHORT 1 R3C3 10 KOHM 1% CH 402 PH1 PH2 PH3 VIN1 VIN2 VIN3 B V_3P3STBY 2 1 VREG_3P3STBY_RT VREG_3P3STBY_SS 0 OHM 5% 1210 EMPTY 1 DB4C5 L4C2 VREG_3P3STBY_COMP_C R3C1 V_VREG_STBY_VIN_CR U3C2 IC TPS54218 ST3C1 SMA 1 EMPTY 1 FT6P2 FTP SMA DIO D4C1 B 2 [PAGE_TITLE=VREGS, STANDBY SWITCHERS] 8 7 MICROSOFT CONFIDENTIAL R5A5 SHOULD BE 182KOHM 0402, WAITING ON COMPONENT TB ADDED IN TC 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 61/72 2 CSA PAGE 61/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 VREGS,STANDBY SWITCHERS 1P1 + 1P8 D D V_1P1STBY NOM.VOLTAGE: 1.13V MAX RECOMMENDED CURRENT: 1.25A FT7P12 FTP DB3C9 1 FTP V_VREG_STBY_VIN IN 2 1 1 C 2 C7P9 10 UF 20% 6.3 V X5R 805 1 1 C7P8 10 UF 20% 6.3 V X5R 805 2 2 1 C3C15 1 C3C16 10 UF 20% 6.3 V EMPTY 805 2 10 UF 20% 6.3 V EMPTY 805 2 20 KOHM 1% 2 CH 402 C7P10 1 UF 10% 6.3 V X5R 402 62 OUT 7 10 KOHM 1% 2 CH 402 FTP FT7R5 6 1 V_VREG_STBY_VIN 1 2 2 R3C29 VREG_1P1STBY_FB COMP 5 VREG_1P1STBY_COMP AGND PGND EN 1 3 1 1 C3C18 4.7 UF 10% 6.3 V X5R 603 1 1 IND SM 1 C3C17 2 DB3C5 0.04 OHM 1.5 UH 2.6 A 2 0.012 UF 10% 16 V X7R 402 C3C21 2 R3C27 1 2 1 1 21.5 KOHM 1% 2 CH 402 VREG_1P1STBY_AGND C3C22 10 UF 20% 6.3 V X5R 805 C7P13 C3C19 1 90.9 KOHM 1% 2 CH 402 1 R3C28 2 1 2 0 OHM 5% 402 EMPTY 470 PF 5% 50 V NPO 402 R3C23 C3C23 1 FTP FT7P14 10 UF 20% 6.3 V X5R 805 10 UF 20% 6.3 V X5R 805 1 2 36.5 KOHM1% CH 402 C7P11 100 PF 5% 50 V EMPTY 402 R3C24 C7P12 10 UF 20% 6.3 V X5R 805 22 UF 20% 6.3 V X7R 805 DB3C6 C DB3C4 FTP FT7P13 ST3C6 VREG_1P1STBY_FB_TOP 2 1 VENABLE SHORT 1 SMA 1 DIO 4 2 10 KOHM 5% 2 EMPTY 402 CR7P2 PG FB ST3C3 IN VSW 1 VREG_1P1STBY_SW X865081-001 SO8 VREG_1P1STBY_EN 61 VIN V_1P1STBY L3C2 8 VREG_1P1STBY_PWRGD 1 1 R7P11 R7P10 U3C4 IC NCP3170 VREG_1P1STBY_COMP_C 61 1 SHORT FT7P9 1 2 CR3C1 B B SMA 1 DIO 2 1 CR7P1 SMA 1 DIO 2 1 C3D6 1 UF 10% 6.3 V EMPTY 402 2 C3D5 1 UF 10% 6.3 V EMPTY 402 FT7P15 FTP 2 CR3C2 SMA 1 DIO FTP 1 NOTE: THIS WAS SET TO 1.83V TO ACCOMODATE DROP IN FERRITES VREG_1P8STBY_IN 1 1 V_3P3STBY CR3C3 2 2 1 C7P6 10 UF 20% 6.3 V EMPTY 805 1 2 100 KOHM 1% 2 EMPTY 402 VREG_1P8STBY_EN C7P5 1 UF 10% 6.3 V X5R 402 1 A 1 2 4 5 U3C3 IC CAT6243DC 4.7 UF 20% 6.3 V X5R 402 VIN EN ADJ GND1 GND2 1 3 6 1 DB3C2 MAX RECOMMENDED CURRENT: 300MA NOM.VOLTAGE: 1.8V 1 2 C3D20 1 V_1P8STBY VOUT X854310-001 DPAK-6 R3D31 0 OHM 5% 2 CH 402 SMA DIO R7P9 V_1P8STBY 1 R3D6 1 OHM 1% 2 CH 402 1 R7R1 1.47 KOHM 1% 2 CH 402 VREG_1P8STBY_COMP_C FT7N1 DB3C10 1 C3D22 C3D21 C3D23 10 UF 20% 6.3 V X5R 805 10 UF 20% 6.3 V X5R 805 1 10 UF 20% 6.3 V EMPTY 805 1 DB3D7 FTP FT7R6 DB3C1 1 A FTP FT7P16 VREG_1P8STBY_FB 1 62 IN R3D30 20 KOHM 1% 2 CH 402 VREG_1P1STBY_PWRGD 1 2 1 R7R2 1.15 KOHM 1% 2 CH 402 C3C9 4.7 UF 10% 6.3 V X5R 603 [PAGE_TITLE=VREGS, STANDBY SWITCHERS] 8 7 MICROSOFT CONFIDENTIAL 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 62/72 2 CSA PAGE 62/72 1 FAB REV M 1.0 8 7 1 2 0 OHM 5% 1210 EMPTY 5 4 EN OUT 1 OC_N 3 1 V_3P3STBY_IR_FLT_N 2 GND 2 R7N3 X862402-001 SOT23-5 100 KOHM 5% 2 CH 402 1 FT7N2 FTP IN 1 26 IN IR BLASTER V_3P3STBY_IR D C7N3 0.1 UF 10% 6.3 V X5R 402 1 1 C5B1 R5B29 1 2 1 KOHM 1% CH 402 IR_BLAST_SMC_OUT 1 R5B1 10 KOHM 5% 2 CH 402 402 3 1 XSTR 2 R5B19 2 1 2 2 402 IR_BLAST_P3_1_R U5B4 IC 74LVC1G00 A 1 B 2 1 2 R5A1 C5A2 0.01 UF 10% 50 V X7R 805 1 2 10 OHM 1% CH 805 R5A2 IR_BLAST_TIP 1 2 0 OHM 5% CH 603 OUT R5A3 Q6B1 NPN IR_BLAST_G1 R5B22 10 KOHM 1% 2 CH 402 1 IR_BLAST_P3_1_IN 2 5 4 IR_BLAST_SLEEVE_R 1 1 IR_JACK_3P IR_BLAST_SLEEVE 4 1 2 1.47 KOHM1% CH 402 MH2 MH1 X852978-004 TH R5B26 3 36 CONN IR_BLAST_TIP_R 2 2 1 2 0 OHM 5% CH 603 Q5B2 1 2 24.9 OHM1% CH 402 DIO 402 J5A2 R5B21 1 2 10 PF 5% 50 V EMPTY 402 1 IR_BLAST_P3_1_OUT J6B2 1X2HDR 2 EG5A1 X882235-001 C5A3 3 3 IR_BLAST_SNUB 0.1 UF 10% 6.3 V X5R 402 1 C5B11 10 UF 20% 10 V X5R 603 C5B13 SC70 IR_BLAST_SENSOR_SIG 1 2 0 OHM 5% EMPTY 402 10 PF 5% 50 V EMPTY 402 5 R5B25 4IR_BLAST_OR_OUT 1 2 3 0 OHM 5% CH 402 VCC Y GND X853473-001 R5B27 PTC 1206 1 X882908-001 V_3P3STBY_IR Q5B1 2 R5B28 C5A1 RT5B12 10 KOHM 1% 1 2 0 OHM 5% CH 402 1 1 V_3P3STBY_IR 1 C V_5P0DUAL 2 10 PF 5% 50 V EMPTY 402 DB3B1 R5B30 4.7 KOHM 1% 2 XSTR R6B11 2 1 IR_BLAST_G2 1 221 OHM 1% CH 1 402 2 C6A1 10 PF 5% 50 V EMPTY 402 1 2 1 1 1 C6A2 10 PF 5% 50 V EMPTY 402 2 0.1 UF 10% 6.3 V X5R 402 V_3P3STBY_IR U3B3 IC TPS2065 C7N2 IR_BLAST_EN IN 2 1 26 3 2 2 4 C EG6A1 X882235-001 DIO 402 IR_BLAST_E1 D 5 IR_BLAST_SMC_OUT_C V_3P3STBY 1 6 R3B2 R6B10 15.8 OHMS 1% 2 CH 805 SM EMPTY IR_BLAST_XIN IC U3C6 B 1 2 70 OUT IC C7N5 1 UF 10% 6.3 V X5R 402 5 VCC 4 Y 3 U3B1 74LVC1G07 A NC GND SC70 X801758-001 2 1 10 KOHM 5% 2 CH 402 A 70 IN IR_BLAST_RXD 475 OHM 1% 2 EMPTY 402 1 1 R7N5 10 KOHM 5% 2 EMPTY 402 5 Y 4 GND 3 OE_N 1 2 X867692-001 SC70-5 D3C2 GREEN SM 2 EMPTY V_3P3STBY_IR VCC A R3C39 1 1 2 0 OHM 5% 402 EMPTY U3B2 IC 74AUP1G125 R7N4 1 R3B3 IR_BLAST_TXD 1 2 2 C7N4 1 UF 10% 6.3 V X5R 402 IR_BLAST_P1_5 V_3P3STBY_IR 1 R3C38 10 KOHM 1% 2 EMPTY 402 IR_BLAST_P0_6 IR_BLAST_P0_5 V_3P3STBY_IR R3C12 1 KOHM 1% EMPTY 402 R3C37 1 2 0 OHM 5% 402 EMPTY V_3P3STBY_IR S3F80P5 V_3P3STBY_IR IR_BLAST_LED V_3P3STBY_IR IR_BLAST_P0_7 TEST VDD 24 XIN 20 19 P3_1/REM/T0CK P3_0/T0PWM/T0CAP/T1CAP/T2CAP 21 P2_0/INT5 18 17 16 15 14 13 12 11 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 10 9 8 7 6 5 4 3 P0_7/INT4 P0_6/INT4 P0_5/INT4 P0_4/INT4 P0_3/INT3 NRESET/P0_2_INT2 SCLK/P0_1/INT1 SDAT/P0_0/INT0 XOUT B 22 1 1 2 1 C3C25 0.1 UF 10% 6.3 V X5R 402 2 C3C26 1 R3C13 10 KOHM 1 UF 10% 6.3 V X5R 402 R7P13 1 2 1 MOHM 5% 402 EMPTY 8 MHZ XTAL Y3C1 XTAL IR_BLAST_XOUT 1 7 3 2 VSS 23 MPAD 25 X854881-001 SM CH X855475-001 QFN25 A R3B4 1 KOHM 1% CH 402 MICROSOFT CONFIDENTIAL 8 1% 2 CH 402 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 63/72 2 CSA PAGE CH 63/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 I2C 66 65 54 53 52 50 44 40 26 IN SMBUS_CLK BI SMBUS_DATA 1 FTP FT4P1 D V_5P0STBY 1 R3E7 0 OHM 5% EMPTY 402 FTP FT4P3 J3E2 2X2HDR 1 3 2 4 I2C_2X2_HDR_VDD 65 44 26 D TH EMPTY C C B B A A MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 64/72 2 CSA PAGE 64/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 FACET, FTDI D D V_3P3STBY C 42 26 29 OUT 27 27 IN 27 OUT OUT OUT OUT 27 OUT 27 27 26 B 27 SMC_RST_N SPI_MISO KER_DBG_TXD IN IN 1 R4E3 1 2 0 OHM 5% CH 402 2 SMC_RST_N_FACET SPI_MISO_FACET SPI_SS_N SPI_CLK SB_TDI SB_TMS SB_TCK SMC_DBG_LED0_SWO_FACET KER_DBG_TXD_FACET KER_DBG_RXD FTDI_SMC_TXD_FACET FTDI_SMC_RXD_FACET SMBUS_CLK_FACET R4E4 1 2 33 OHMS 1% CH 402 R4E5 1 2 33 OHMS 1% CH 402 C4E1 1 C4E2 1 UF 10% 6.3 V X5R 402 2 1 UF 10% 6.3 V X5R 402 R4D1 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 1 2 33 OHMS 1% CH 402 SPI_MOSI KER_DBG_CTS KER_DBG_RTS_FACET FTDI_SMC_CTS_FACET FTDI_SMC_RTS_FACET R4E1 1 2 33 OHMS 1% CH 402 SMBUS_DATA_FACET BI KER_DBG_RTS 1 1 R5T1 SMBUS_CLK OUT 27 IN 27 OUT 27 IN 27 SB_TDO_FACET 1 DB4E4 SB_TDO SM EMPTY 1 DB4E3 66 64 54 53 52 50 40 44 26 C J4E1 2X13HDR SMC_DBG_LED0_SWO IN R4E2 1 2 100 OHM 1% CH 402 1 2 0 OHM 5% CH 402 R5T2 1 2 0 OHM 5% CH 402 SMBUS_DATA B DB4E1 DB4E2 BI 26 40 44 50 52 53 54 64 66 A A MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 65/72 2 CSA PAGE 65/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 FACET, FTDI+MISC D D V_3P3STBY C C C5U10 1 R5U4 1 0 OHM 5% 2 EMPTY 402 65 44 26 DEBUG R5U5 0 OHM 5% 2 EMPTY 402 EEPROM_A2 EEPROM_A1 IN 3 2 SMBUS_CLK 6 7 CAT24M01 I2C ADDRESSES 1010 110 R/W HEX WRITE 1010 110 0 0XAC READ 1010 110 1 0XAD B 1010 111 WRITE 1010 111 READ 1010 111 U5F4 CAT24M01 EMPTY A2 A1 SCL WP VCC 0.1 UF 10% 6.3 V EMPTY 402 1 2 1 2 C5U9 1 UF 10% 6.3 V EMPTY 402 8 SDA 5 NC VSS MPAD 1 4 9 SMBUS_DATA BI 26 40 44 50 52 53 54 64 65 X868479-001 DFN9 B R/W HEX 0 0XAE 1 0XAF A A MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 66/72 2 CSA PAGE 66/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 CONN, SWITCHES D D V_12P0 V_5P0STBY 1 EJECTSW_N_SW R4F21 1 EJECTSW_N 2.49 KOHM 1% CH 402 40 26 1 2 C V_12P0_LED_R V_5P0STBY_LED_R J4F4 1X2HDR OUT TH EMPTY R8B17 6.04 KOHM 1% 2 EMPTY 402 R8B18 2 KOHM 1% 2 EMPTY 402 C 1 1 PWRSW_N_SW R4F20 2.49 KOHM 1% CH 402 D8B1 GREEN SM 2 EMPTY D8B2 GREEN SM 2 EMPTY PWRSW_N OUT 40 26 J4F5 1X2HDR 1 2 TH EMPTY B B A A MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 67/72 2 CSA PAGE 67/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 CONN, HDT D D V_SOC1P8 1 R5E14 1 1 KOHM 1% EMPTY 2 402 V_SOC1P8 C 1 R5E17 1 V_SOC1P8 FT5T1 FTP 1 1 R5E4 2 1 KOHM 5% 2 CH 402 8 C5E1 1 UF 10% 6.3 V EMPTY 402 1 2 C5T6 0.1 UF 10% 6.3 V EMPTY 402 1 2 R5E3 1 2 0 OHM 5% 402 EMPTY OUT TRST_L DEBUG FT5T2 FTP 0.1 UF 10% 6.3 V EMPTY 402 HDT_PIN11 HDT_PIN13 HDT_PIN15 R5D8 1 10 KOHM 5% 2 EMPTY 402 R5E2 10 KOHM 5% 2 EMPTY 402 2 4 6 8 10 12 14 16 18 20 1 3 5 7 9 11 13 15 17 19 1 4 1 2 COLD_RESET_N OUT J4F2 1X2HDR SM 1 1 2 2 TH EMPTY 1 EMPTY U6E1 SN74AUP2G07 1 26 R3F2 47 KOHM 1% 2 EMPTY 402 X802100-002 A SW4F1 2 4 WARM_RESET_N 1 2 2 1 J4F1 1X2HDR SM 1 2 2 C4F19 1 0.22 UF 10% 6.3 V EMPTY 402 IN OUT OUT OUT 8 8 70 8 70 8 1 3 2 VCC 5 1A 1Y 6 2A 2Y 4 GND 2 C6E1 0.22 UF 10% 6.3 V EMPTY 402 B 1 R5E16 1 R5E15 1 KOHM 1 KOHM 5% 5% 2 EMPTY 2 EMPTY 402 402 IN SOC_PWR_OK C6E2 0.22 UF 10% 6.3 V EMPTY 402 EMPTY U4F4 SN74AUP1G17 EMPTY 3 8 8 8 8 X865298-001 SC70-6 V_SOC1P8 1 OUT OUT OUT IN FTP FT5T6 R5E1 C4F18 V_SOC1P8 FTP FT5T3 V_SOC1P8 10 KOHM 5% 2 EMPTY 402 26 0.22 UF 10% 6.3 V EMPTY 402 1 TCK TMS TDI TDO PWROK_BUF RESET_L_BUF DBRDY DBREQ_L TEST19 TEST18 C FTP FT4T2 1 EMPTY 3 1 1 SM EMPTY X802100-002 SW4F2 1 KOHM 1% 2 EMPTY 402 J5E1 2x10HDR_HDT HDT_TRST 1 B C5T4 R5E18 1 KOHM 1% 2 EMPTY 402 1 R5E19 1 KOHM 1% 2 EMPTY 402 A NC X862374-001 SC70-5 V_SOC1P8 VCC 5 Y 4 GND 3 U6E2 EMPTY 74LVC1G07 WARM_RESET_N_DEBOUNCE 2 A 1 NC X801758-001 VCC 5 Y 4 GND 3 A SOC_RST_N OUT 26 8 SC70 TH EMPTY MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 68/72 2 CSA PAGE 68/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 DEBUG, VR HEADERS AND TEST POINTS D D V_CPUCORE V_GFXCORE EMPTY V_NBCORE EMPTY TP9F1 EMPTY EMPTY EMPTY EMPTY EMPTY TP9C1 EMPTY EMPTY V_VTTC V_VTTA EMPTY EMPTY V_3P3STBY EMPTY EMPTY TP6D2 1 EMPTY 1 1 EMPTY EMPTY V_MEMIOCD TP6C1 1 B EMPTY 1 EMPTY TP5B1 EMPTY TP5C1 1 EMPTY EMPTY TP3D2 1 EMPTY 1 EMPTY EMPTY TP3D3 1 TP9F4 1 EMPTY V_SB1P1 EMPTY EMPTY TP4B2 EMPTY EMPTY TP4D3 1 TP4D2 1 V_SB1P1 EMPTY EMPTY TP5D1 1 EMPTY TP3F1 TP4E1 1 EMPTY C EMPTY TP6D1 V_BAT EMPTY EMPTY V_1P8STBY EMPTY EMPTY TP8B1 EMPTY 1 V_SOC1P8 TP4B3 1 EMPTY EMPTY V_12P0 TP4C1 1 EMPTY EMPTY EMPTY TP6E1 EMPTY 1 1 V_SB1P8 TP5D2 1 V_5P0STBY V_FUSE TP4B1 1 TP3C1 1 EMPTY EMPTY EMPTY TP3E3 1 TP5C2 1 V_SOC1P8 EMPTY TP5F1 1 EMPTY EMPTY TP6D4 1 V_5P0DUAL EMPTY TP9F3 1 EMPTY V_1P1STBY EMPTY TP4F4 1 V_5P0 V_SB1P8 EMPTY TP5E2 1 V_3P3 V_VTTB V_BURN EMPTY TP6F1 1 V_VTTD V_SOCPHY EMPTY TP9C2 1 C V_MEMCORE EMPTY 1 EMPTY EMPTY EMPTY EMPTY EMPTY B EMPTY TP3E2 EMPTY 54 IN VREG_V5P0_PWRGD OUT IN OUT VREG_PWRGPB_PWRGD IN A OUT VREG_PWRGPB_EN IN EMPTY TP6F2 1 EMPTY EMPTY TP8B2 1 EMPTY 1 EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY 1 EMPTY TP4F1 VREG_PWRGPA_PWRGD 1 EMPTY TP4F2 VREG_PWRGPA_EN 1 A EMPTY TP7C1 EMPTY 45 44 EMPTY EMPTY TP4F3 EMPTY 56 53 52 26 TP4D1 1 1 EMPTY 56 53 52 TP5E1 1 EMPTY TP4F5 EMPTY 58 57 51 50 26 1 1 EMPTY 57 51 50 TP9F2 EMPTY TP3E1 VREG_V5P0_EN TP4C2 EMPTY 1 EMPTY 54 26 V_MEMIOAB VREG_CPUGFX_PWRGD 1 EMPTY MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 69/72 2 CSA PAGE 69/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 DEBUG, CONNECTORS D D TITAN POWER CONNECTOR V_3P3STBY DEBUG J3C2 1X2HDR 1 2 TH EMPTY C C V_SOCPHY 1 DB4D2 63 IN 1 FTDI_SMC_CTS R6R11 1 100 OHM 5% CH 2 R6R8 1 1 R6R9 402 100 OHM 100 OHM 5% 5% CH 2 2 EMPTY 402 402 IR_BLAST_RXD FTDI_SMC_RTS 1 IR_BLAST_TXD 1 OUT R5F31 510 OHM 5% 2 CH 402 63 DB4D3 R6R10 100 OHM 5% 2 EMPTY 402 2 B 2 IN IN TEST25_N B TEST25_P 1 1 26 26 26 26 BI BI BI BI R5F27 510 OHM 5% 2 CH 402 SMC_TXD SMC_RTS SMC_CTS SMC_RXD R5E7 1 KOHM 5% 2 EMPTY 402 1 TEST19 OUT 68 8 TEST18 OUT 68 8 R5E8 1 KOHM 5% 2 EMPTY 402 A A MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 2 PROJECT NAME GREYBULL_RETAIL PAGE 70/72 CSA PAGE 70/72 1 REV 1.0 8 7 6 5 4 3 2 1 DEBUG, ENET EEPROM + MISC D D C C V_3P3STBY_ENET 1 2 U5B1 EMPTY 93LC66B B 32 IN ENET_EEDI 3 DI 32 IN ENET_EESK 2 CLK 32 IN ENET_EECS 1 CS VCC 8 DO 4 NC1 NC2 GND 6 7 5 ENET_EEDO C5B3 0.1 UF 10% 6.3 V EMPTY 402 OUT 32 B X867158-001 TSSOP8 A A MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 71/72 2 CSA PAGE 71/72 1 FAB REV M 1.0 8 7 6 5 4 3 2 1 LABELS AND MOUNTING D D HEAT SINK MOUNTING HOLES STD STD MTG8D1 MTG7E1 MTG_HOLE NC9 9 MTG_HOLE NC9 9 EMPTY GND=1,2,3,4,5,6,7,8 C EMPTY GND=1,2,3,4,5,6,7,8 STD C STD MTG8E1 MTG7D1 MTG_HOLE NC9 9 MTG_HOLE NC9 9 EMPTY GND=1,2,3,4,5,6,7,8 EMPTY GND=1,2,3,4,5,6,7,8 B B INTELLIGENT SERIAL NUMBER TARGET X801181-001 LB3F1 1 LABEL 1375X250_TARGET A A MICROSOFT CONFIDENTIAL 8 7 6 5 4 3 PROJECT NAME PAGE GREYBULL_RETAIL 72/72 2 CSA PAGE 72/72 1 FAB REV M 1.0